Director, Engineering, Analog Mixed-Signal - Mountain View, CA, United States
$281,000 - $391,000 USD yearly
Originally posted 15 October 2026 by the employer.
Define the future of PHY IP for Tensor and Pixel platforms.
About the role
As the Director of Analog Mixed-Signal Silicon, you will lead the strategy and execution of mixed-signal IP development for Google's consumer hardware products. This role will define the multi-generational AMS strategy to establish a competitive advantage for platforms like Tensor and Pixel and optimize the next three generations of Tensor SoCs.
What you'll do
- Lead the critical "make vs. buy" decision for the future of DDR PHY IP and define the multi-year AMS roadmap for SoCs.
- Own the overall Power, Performance, and Area (PPA) envelope for the entire memory subsystem, dictating trade-offs and ensuring DDR access meets the requirements of on-device GenAI models.
- Direct the integrated AMS and PMIC teams, ensuring high-quality execution of the immediate optimization roadmap.
- Build the talent and organizational structure required for the long-term strategic vision.
- Act as the technical and strategic liaison to executive leadership, driving organizational alignment and securing resource commitments.
What you'll need
- Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
- 15 years of experience with custom silicon design (SoCs, ASICs, etc.).
- 10 years of experience in people management and developing employees.
- Experience in high-speed analog mixed-signal design, specifically in DDR PHY/LPDDR interfaces.
- Experience with analog and digital mixed-signal design (AMS, DMS).
Nice to have
- Master's degree or PhD in Electrical Engineering, or a related field.
- 10 years of experience with analog and digital mixed-signal design with a deep understanding of both disciplines.
- Experience leading cross-functional IP development and SoC integration.
- Experience with process nodes in silicon foundries.
- Experience across silicon engineering topics from architecture and implementation to productization and high-volume manufacturing.
- Understanding of the systemic challenges related to power, performance, and thermal management in mobile and AI SoCs.
Skills: DDR PHY, LPDDR interfaces, high-speed analog mixed-signal, AMS, PPA
This role has been open 0 days — well below the 78-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
78 d
|
Median salary
$176k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | All employers we track in this specialty (241 roles · 47 employers) | |
|---|---|---|
| Open roles in this specialty | 1 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 1 | 1414 · 106 employers |
| Median days open | 0 d | 78 d (−78 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Skills observed across this category: DDR PHY, LPDDR interfaces, high-speed analog mixed-signal, AMS, PPA
Who's hiring in this category
- Synopsys · 31 open roles · median 30 d
- AMD · 30 open roles · median 39 d
- Cadence Design Systems · 19 open roles · median 188 d
- Qualcomm · 19 open roles · median 57 d
- Micron Technology · 14 open roles · median 53 d
- Apple · 12 open roles · median 16 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.