Director, Design Verification - San Jose, California, United States
$219,000 - $351,000 USD yearly
Originally posted 13 May 2026 by the employer.
About the role
As Director, Design Verification, you will be responsible for the end-to-end verification of SoCs and manage an engineering team driving first-pass silicon success. The role sits within the DRAM Development Lab (DDL) SOC team, focusing on silicon solutions such as Custom HBM base die and AI accelerators.
What you'll do
- Define and implement SoC verification strategy and methodology. - Lead the verification team to successful verification signoffs across multiple concurrent projects. - Plan and manage resource allocations, complex project schedules, and risk mitigations. - Define and enhance development milestones and verification flows for SoC projects. - Work closely with Architecture, Design, FW, and Validation counterparts to align on verification requirements and targets. - Provide support in post-silicon bring up and debug.
What you'll need
- BE or MS in Computer Engineering, Electrical Engineering, or Computer Science, with 15+ years of ASIC verification experience. - Several years of proven leadership managing verification teams across multiple successful tape-outs. - Expert-level knowledge and hands-on experience in UVM, C++, and SystemVerilog. - Expert-level knowledge of verification flows and EDA tools. - Demonstrated ability to manage complex project schedules, resource allocations, and risk mitigations. - Experience coordinating with architecture, design, firmware, and validation teams through post-silicon bring up.
Skills: SoC verification, UVM, SystemVerilog, tape-outs, memory
This role has been open 163 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (1254 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1254 |
| Open roles in the wider Digital Design & Verification family | 14 | 3328 · 115 employers |
| Median days open | 115 d | 64 d (+51 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SoC verification, UVM, SystemVerilog, tape-outs, memory
Who's hiring in this category
- Qualcomm · 120 open roles · median 43 d
- AMD · 94 open roles · median 53 d
- NVIDIA · 84 open roles · median 65 d
- Synopsys · 67 open roles · median 39 d
- SiFive · 55 open roles · median 81 d
- Cadence Design Systems · 52 open roles · median 123 d
How we counted: 1254 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.