Director ASIC Technical Program Management - San Jose, California, United States
$210,000 - $275,000 USD yearly
Originally posted 15 October 2026 by the employer.
About the role
This role involves leading a team of Technical Program Managers (TPMs) to ensure the execution framework for advanced ASIC programs from early planning through production release, while also directly leading programs when needed.
What you'll do
- Lead the US-based TPM team, owning the cross-functional execution framework for advanced ASIC programs.
- Drive milestone planning, dependency management, execution reviews, decision-making forums, and risk mitigation.
- Ensure program readiness at key gates, including tapeout, power-on, and production release.
- Bring consistency and clarity to program status reporting for executive leadership and the PLM team.
- Partner directly with external partners and customers as a senior representative of the program.
What you'll need
- BS or MS in Electrical, Electronics, or Computer Engineering.
- 15+ years of ASIC product development experience in a semiconductor environment.
- Strong understanding of ASIC development flows, with hands-on experience in RTL, DSP, or Physical Design.
- Experience delivering ASICs in advanced nodes.
- Proven ability to lead in a matrixed environment.
- Strong program management and leadership skills.
Skills: ASIC program lifecycle, tapeout, post-silicon validation, risk mitigation, cross-functional leadership
This role has been open 1 day — well below the 46-day median for Technical Program Management roles.
Technical Program Management · SOC Architecture
|
Open roles in category
175
|
Median days open
46 d
|
Median salary
$219k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (175 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 175 |
| Median days open | 67 d | 46 d (+21 d vs this employer) |
| Median salary (USD postings) | — | $219k |
Skills observed across this category: ASIC program lifecycle, tapeout, post-silicon validation, risk mitigation, cross-functional leadership
Who's hiring in this category
- Qualcomm · 26 open roles · median 51 d
- AMD · 20 open roles · median 29 d
- NVIDIA · 18 open roles · median 41 d
- Synopsys · 14 open roles · median 45 d
- Arm Holdings · 10 open roles · median 82 d
- Apple · 7 open roles · median 66 d
How we counted: 175 open Technical Program Management (SOC Architecture) roles from 47 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.