Digital Verification Engineer - Shanghai, Pudong, ZuChongzhi, China
Originally posted 22 September 2026 by the employer — open 0 days.
This role focuses on the full Metric Driven Verification (MDV) flow across mixed-signal ICs and large-scale SoCs.
About the role
This role involves ensuring digital and mixed-signal products behave as specified before silicon. You will contribute to the full Metric Driven Verification (MDV) flow across mixed-signal ICs and large-scale SoCs with embedded processors.
What you'll do
- Analyze specifications to define verification scope, features, and coverage goals.
- Build and maintain block- and system-level environments using SystemVerilog, UVM, or C++.
- Create test cases, run regressions, and drive functional and coverage closure.
- Investigate failures across RTL, testbench, and system boundaries, and resolve them with the design team.
- Support formal verification, directed testing, and FPGA-based validation.
What you'll need
- Solid understanding of digital logic design and the IC design flow.
- Familiarity with SystemVerilog, UVM, or C++ and simulation-based verification concepts.
- Ability to reason about what “correct behavior” means for a specification.
- Capacity to question results and cross-check against the spec or an independent method.
- Curiosity and ability to pick up unfamiliar tools quickly.
- Strong collaboration and sufficient English for daily communication and technical documents.
Nice to have
- Master’s degree or above in electronics, microelectronics, computer science, mathematics, physics, or automation.
- Scripting skills (Python, Perl, Tcl).
- Hands-on experience with AI coding assistants or agentic development tools.
- Background in AI/ML relevant to edge deployment (inference, quantization, real-time constraints, or AI hardware acceleration).
- Exposure to formal verification, SVA, or coverage closure.
- Familiarity with AXI/AHB/APB or other bus protocols and verification IP.
- Experience with closed-loop control systems (e.g., PID, temperature or power management).
- Experience with analog/mixed-signal co-simulation and verification methodology.
- Experience with system-level integration verification across multiple subsystems, or functional safety.
Skills: SystemVerilog, UVM, testbench development, functional coverage, mixed-signal ICs
This role has been open 0 days — well below the 60-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1150
|
Median days open
60 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Analog Devices | All employers we track in this specialty (1150 roles · 94 employers) |
|---|---|---|
| Open roles in this specialty | 38 | 1150 |
| Open roles in the wider Digital Design & Verification family | 96 | 3066 · 114 employers |
| Median days open | 55 d | 60 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: SystemVerilog, UVM, testbench development, functional coverage, mixed-signal ICs
Who's hiring in this category
- Qualcomm · 106 open roles · median 50 d
- AMD · 102 open roles · median 34 d
- NVIDIA · 89 open roles · median 68 d
- Synopsys · 62 open roles · median 17 d
- Micron Technology · 54 open roles · median 101 d
- SiFive · 52 open roles · median 49 d
How we counted: 1150 open Design Verification (Design Verification) roles from 94 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.