Digital Verification Engineer (MTD, San Jose, CA)
$135,400 - $216,600 USD yearly
Originally posted 17 July 2026 by the employer.
About the role
Digital functional verification engineers are responsible for the planning, strategy, and execution of FPGA verification projects under the technical supervision of a Verification Lead. The position requires interfacing with hardware, software, and applications teams.
What you'll do
- Lead the planning, strategy, and execution of FPGA verification projects under the technical supervision of a Verification Lead. - Interface with cross-functional groups including hardware, software, and applications. - Develop and integrate UVM testbench components, test sequences, and reference models/predictors. - Build verification test plans using tools such as Cadence ePlanner. - Execute SystemVerilog constraint random testing, assertions, and functional coverage closure. - Integrate Verification IP and verify industry standard protocols such as AXI, PCIe, and DDR3/4/5.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field with 8+ years of relevant experience, or a Master's degree with 6+ years of relevant experience. - Experience with Verification Test Plan tools (e.g., Cadence ePlanner) and EDA tools (e.g., Cadence Xcelium, Simvision). - Experience with SystemVerilog constraint random testing, assertions, and functional coverage. - Experience developing and integrating UVM testbench components, test sequences, and reference models/predictors. - Expertise with Verification IP integration and industry standard protocols (e.g., AXI, PCIe, DDR3/4/5). - Experience working with revision source control tools such as ClearCase, Git, or SVN.
Nice to have
- Experience in FPGA design implementation with SystemVerilog. - Experience in verification of Automated Test Equipment functionality. - Experience writing automation scripts (e.g., Makefiles, shell programming, TCL, Perl, Python).
Skills: digital verification, SystemVerilog, UVM, functional verification, testbench
This role has been open 95 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1220
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (1220 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1220 |
| Open roles in the wider Digital Design & Verification family | 9 | 3261 · 116 employers |
| Median days open | 95 d | 64 d (+31 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: digital verification, SystemVerilog, UVM, functional verification, testbench
Who's hiring in this category
- Qualcomm · 114 open roles · median 41 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 62 d
- Synopsys · 65 open roles · median 36 d
- SiFive · 55 open roles · median 78 d
- Cadence Design Systems · 50 open roles · median 120 d
How we counted: 1220 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.