Digital Verification Engineer
$130,000 - $180,000 USD yearly
Originally posted 22 October 2026 by the employer.
About the role
As a Digital Verification Engineer, you will own the functional verification of blocks and subsystems in the SoC, including Efficient's proprietary Fabric technology. You will work alongside DV engineers, RTL designers, and architects to build testbenches, close coverage, and identify bugs before silicon tapeout.
What you'll do
- Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests for block- and subsystem-level verification. - Write verification plans from design specifications in collaboration with design and architecture teams. - Write SystemVerilog assertions and functional coverage models, and drive coverage to closure. - Debug simulation failures, working with designers to root-cause and fix issues. - Contribute to regression infrastructure, automation, and dashboards that track verification progress. - Support gate-level simulation and other sign-off activities.
What you'll need
- Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field. - 4+ years of experience in ASIC/SoC design verification, with multiple projects taken through tapeout. - Hands-on experience building and extending UVM testbench components (agents, scoreboards, sequences) and constrained-random tests. - Experience defining functional coverage and driving code and functional coverage closure at the block or subsystem level. - Working knowledge of SystemVerilog Assertions. - Demonstrated ability to independently debug simulation failures using waveforms, logs, and design knowledge, alongside proficiency in Python for test automation, log analysis, and regression flows.
Nice to have
- C/C++ experience for reference models or DPI-based verification. - Exposure to formal verification (JasperGold or similar). - Experience building or using AI agentic flows for DV. - Knowledge of computer architecture or dataflow architectures. - Exposure to power-aware verification (UPF).
Skills: UVM, SystemVerilog, assertions, functional coverage, regression
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1233
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Efficient Computer | All employers we track in this specialty (1233 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1233 |
| Open roles in the wider Digital Design & Verification family | 7 | 3298 · 115 employers |
| Median days open | 30 d | 64 d (−34 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, assertions, functional coverage, regression
Who's hiring in this category
- Qualcomm · 115 open roles · median 41 d
- AMD · 93 open roles · median 51 d
- NVIDIA · 84 open roles · median 62 d
- Synopsys · 66 open roles · median 37 d
- SiFive · 55 open roles · median 79 d
- Cadence Design Systems · 51 open roles · median 121 d
How we counted: 1233 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.