Digital IC Design Engineer, Intern - Pavia, Italy
$21,250 - $28,750 USD yearly
Originally posted 9 September 2026 by the employer.
This role focuses on developing high-speed PAM/Coherent DSPs and PHY designs.
About the role
This internship involves performing digital design tasks and optimizing high-speed parallel DSP architectures. You will contribute to the development of Marvell's high-speed PAM/Coherent DSPs and PHY designs utilizing CMOS technology.
What you'll do
- Perform digital design tasks using HDL design, digital verification, DFT design, synthesis, static timing analysis, and power analysis tools. - Code in scripting languages such as TCL, Perl, Python, and Unix shell. - Work on optimizing and simulating high-speed parallel DSP architectures. - Analyze and explore parallel DSP optimization challenges and solutions. - Collaborate with cross-functional teams (architecture, validation, software) to optimize device solutions.
What you'll need
- Final-year Master’s student in Electronics, Software Engineering, Mathematics, Physics, or a similar technical field at an accredited Italian university or a recent master’s graduate. - Bachelor’s degree in Electrical Engineering, Software Engineering, or a related field. - Basic knowledge of digital design. - Strong written and verbal communication skills in English.
Nice to have
- Basic knowledge of design verification and DFT (Design for Test). - Knowledge of digital signal processing.
Skills: HDL design, DSP architectures, synthesis, static timing analysis, DFT
This role has been open 47 days — well below the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1081
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (1081 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 1081 |
| Open roles in the wider Digital Design & Verification family | 37 | 3328 · 116 employers |
| Median days open | 39 d | 66 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: HDL design, DSP architectures, synthesis, static timing analysis, DFT
Who's hiring in this category
- Qualcomm · 158 open roles · median 63 d
- Synopsys · 86 open roles · median 40 d
- AMD · 77 open roles · median 45 d
- Analog Devices · 49 open roles · median 56 d
- NXP Semiconductors · 44 open roles · median 100 d
- NVIDIA · 37 open roles · median 52 d
How we counted: 1081 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.