Digital Design Verification, Principal Engineer / Architect-17853
Originally posted 11 June 2026 by the employer.
About the role
Synopsys is seeking a Principal Engineer / Architect to build robust, scalable verification infrastructures and unified verification flows for digital IP and SoC projects. The role is part of the Digital IP Verification Methodology (COE) team and focuses on applying agentic AI tools and Synopsys EDA tools to streamline verification processes.
What you'll do
- Apply agentic AI tools to generate verification plans, testcases, coverage, and debug collaterals. - Implement reference and unified verification flows for Synopsys digital IP products using EDA tools including VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs. - Build verification infrastructures from the ground up to support diverse IP and SoC projects. - Partner with global engineering teams to define, document, and propagate verification methodologies and standards. - Collaborate with tool development teams to influence product evolution and optimize verification workflows. - Lead and mentor junior engineers, driving technical initiatives and managing high-impact assignments independently.
What you'll need
- Minimum 12+ years of hands-on experience in IP/SoC verification with a proven track record of technical contributions. - Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering. - Understanding of Agentic AI technologies, specifically Cursor or VS Code co-pilot. - Familiarity with Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs. - Solid programming and scripting skills in SystemVerilog, UVM, Tcl, Python, or similar languages. - Demonstrated ability to validate verification flows and infrastructure for complex digital designs.
This role has been open 125 days — well above the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1078
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1078 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 88 | 1078 |
| Open roles in the wider Digital Design & Verification family | 176 | 3297 · 115 employers |
| Median days open | 36 d | 63 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 157 open roles · median 59 d
- Synopsys (this employer) · 88 open roles · median 36 d
- AMD · 76 open roles · median 41 d
- Analog Devices · 49 open roles · median 52 d
- NXP Semiconductors · 42 open roles · median 91 d
- NVIDIA · 40 open roles · median 63 d
How we counted: 1078 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.