Digital Design (Physical) Engineer - Beijing, Haidian, Xixiaokou, China
Originally posted 22 September 2026 by the employer — open 0 days.
This role focuses on the RTL-to-GDSII flow for digital and mixed-signal products.
About the role
This role involves learning and contributing to the RTL-to-GDSII flow for digital and mixed-signal products. You will work on floor planning, placement, clock tree synthesis, routing, and timing closure tasks on real production designs.
What you'll do
- Contribute to the RTL-to-GDSII flow, including floorplanning, power planning, placement, clock tree synthesis (CTS), and routing.
- Run static timing analysis (STA) across PVT corners in multi-corner multi-mode (MCMM) setups and resolve setup/hold violations.
- Support power delivery network (PDN) work, including IR-drop and electromigration (EM) analysis.
- Run DRC, LVS, antenna, and ERC checks and drive issues to clean signoff.
- Work with analog layout engineers on floorplan co-optimization and constraints at sensitive analog/digital boundaries.
- Script and automate repetitive physical design tasks to improve the team's flow.
What you'll need
- Solid understanding of digital logic, CMOS basics, and the IC design flow.
- Working understanding of static timing analysis, setup/hold, and clock domain crossing (CDC).
- Experience with digital implementation tools (Cadence Genus/Innovus/Tempus or an equivalent flow).
- Ability to write Tcl, Python, or shell scripts to automate repetitive tasks.
- Strong collaboration with design and layout teams, and sufficient English for daily communication and technical documents.
Nice to have
- Master's degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
- Tape-out experience from a university project or internship.
- Exposure to power analysis (IR-drop, EM) or power intent specification (UPF/CPF).
- Exposure to DFT methodologies (scan insertion, compression, ATPG, JTAG/boundary scan).
- Familiarity with mature analog process nodes (e.g., 180nm BCD) and advanced digital nodes.
- Experience using AI tools to improve flow development or engineering productivity.
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
943
|
Median days open
62 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Analog Devices | All employers we track in this specialty (943 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 45 | 943 |
| Open roles in the wider Digital Design & Verification family | 96 | 3066 · 114 employers |
| Median days open | 63 d | 62 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Qualcomm · 144 open roles · median 55 d
- AMD · 62 open roles · median 63 d
- Synopsys · 56 open roles · median 19 d
- NXP Semiconductors · 52 open roles · median 69 d
- NVIDIA · 48 open roles · median 46 d
- Analog Devices (this employer) · 39 open roles · median 75 d
How we counted: 943 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.