DFT, Principal Engineer

Originally posted 5 October 2026 by the employer.

Define and execute test strategies for complex SoCs across scan/ATPG, memory BIST, and logic BIST.

About the role

This role involves owning DFT architecture, implementation, integration, and verification for complex SoCs and subsystems from specification through tapeout.

What you'll do

• Own DFT architecture, implementation, integration, and verification for complex SoCs and subsystems.
• Define and execute test strategies across scan insertion and ATPG, memory BIST, logic BIST, and analog/PHY test considerations.
• Drive DFT signoff readiness by identifying testability risks and proposing design changes.
• Develop and institutionalize reusable DFT methodologies, checklists, and guidelines using Synopsys EDA tools.
• Partner with silicon validation and test engineering teams on post-silicon debug, failure analysis triage, and pattern refinement.
• Collaborate closely with RTL design, functional verification, physical design, timing, and power teams to ensure testability.

What you'll need

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or related field.
• Typically 10+ years of hands-on SoC DFT experience with depth in scan/ATPG, memory BIST, logic BIST, and analog test considerations.
• Strong understanding of the end-to-end SoC design flow from microarchitecture through RTL, verification, synthesis, timing/physical implementation, and signoff.
• Demonstrated experience owning DFT implementation for complex SoCs that have taped out and gone to production.
• Proven ability to work cross-functionally to resolve testability issues and drive closure under schedule constraints.

Nice to have

• Strong working knowledge of Synopsys DFT tools such as TetraMAX, DFT Compiler, and BIST Architect.
• Post-silicon debug experience and collaboration with test engineering teams to refine production test programs.