DFT Intern - Singapore

Originally posted 1 October 2026 by the employer.

About the role

This role is for a Design for Test (DFT) Intern to join the SoC team, contributing to scan and MBIST implementation and verification. The position focuses on ultra-low power chips, offering hands-on experience with industry-standard DFT tools and methodologies.

What you'll do

• Support low power DFT implementation and verification for SoC designs
• Assist with scan insertion and scan chain verification for physical design modules
• Assist with MBIST insertion and verification for embedded memories
• Analyze DFT rule checking results and help resolve design and testability issues
• Support test coverage analysis and identify opportunities for coverage improvement
• Develop and maintain scripts (e.g., Tcl, Python, Shell) to automate recurring tasks

What you'll need

• Currently pursuing a B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
• Completed coursework in Digital logic design, VLSI design / ASIC design, or CMOS circuits
• Familiarity with Verilog, SystemVerilog or VHDL
• Familiarity with fundamental digital design concepts such as timing, clocking, reset, and pipelining
• Comfortable working in a Linux/UNIX environment
• Strong analytical, debugging, and problem-solving skills

Nice to have

• Experience with industry-standard EDA tools for scan insertion, ATPG, MBIST, memory repair, or embedded memory testing
• Basic understanding of DFT concepts such as scan, ATPG, MBIST, fault coverage, and memory repair
• Scripting experience in Tcl, Python, or Shell for flow automation
• Familiarity with fault models such as stuck-at, transition, bridging, memory faults
• Understanding of low power design concepts such as multiple power domains, retention, or clock gating