DFT Intern - San Jose, United States
Originally posted 13 April 2026 by the employer.
About the role
As a DFT Intern at Etched, you will review and refine DFT flow automation to support chip-level regression on Caelius.
What you'll do
- Review and refine DFT flow automation to support chip-level regression on Caelius. - Work across frontend and backend design teams. - Contribute to DFT verification, including MBIST, Scan, BSCAN, and SSN simulations. - Develop flows for various ATPG fault models.
What you'll need
- Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field. - Familiarity with a hardware description language such as Verilog or SystemVerilog. - Exposure to ASIC or SoC design concepts and standard ASIC design flow steps (synthesis, STA, DFT). - Familiarity with digital logic design fundamentals. - Familiarity with scripting in Python, Tcl, or another language.
Skills: DFT flow automation, MBIST, Scan, BSCAN, ATPG
This role has been open 191 days — well above the 61-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
248
|
Median days open
61 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (248 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 248 |
| Open roles in the wider Digital Design & Verification family | 13 | 3299 · 116 employers |
| Median days open | 205 d | 61 d (+144 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Skills observed across this category: DFT flow automation, MBIST, Scan, BSCAN, ATPG
Who's hiring in this category
- AMD · 39 open roles · median 43 d
- NVIDIA · 24 open roles · median 31 d
- Qualcomm · 23 open roles · median 105 d
- NXP Semiconductors · 19 open roles · median 45 d
- Synopsys · 15 open roles · median 28 d
- Intel Corporation · 10 open roles · median 62 d
How we counted: 248 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.