DFT Engineer - Palo Alto

Originally posted 13 October 2026 by the employer.

About the role

You will own DFT end to end, covering DFT architecture and insertion, MBIST planning, fault-model analysis, and ATPG signoff in pre-silicon, through hands-on CP, FT, and SLT bring-up in post-silicon.

What you'll do

- Own DFT architecture and insertion for silicon at advanced nodes, including hierarchical scan and compression, BIST, MBIST and BISR planning, boundary scan, and IJTAG networks. - Define fault-model and coverage strategies across stuck-at, transition, path-delay, cell-aware, and bridging faults, owning ATPG generation, fault simulation, coverage closure, and SDF gate-level simulation signoff. - Drive post-silicon test from first silicon to production, leading ATE pattern conversion, CP, FT, and SLT program bring-up, scan diagnosis, failure analysis, and yield improvement with foundry and OSAT partners. - Integrate DFT with RTL, DV, and physical design by setting micro-architectural requirements, verifying test logic, closing test-mode timing with STA, and contributing directly to RTL or DV when needed. - Partner cross-functionally on chip design infrastructure and automation, encoding DFT methodology into reusable flows, checks, and evaluation targets.

What you'll need

- BS in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field. - 5+ years of hands-on DFT experience across the full lifecycle on complex SoCs or IPs, including scan compression, MBIST, BISR, boundary scan, IJTAG, test-mode timing constraints, DRC closure, and ATPG pattern signoff. - Fluency in at least one production DFT stack and gate-level simulation, along with Tcl, Python scripting, and Verilog/SystemVerilog for test logic and testbench debug. - Post-silicon experience taking silicon to production, including bring-up of ATPG and MBIST patterns on ATE, debugging CP, FT, and SLT failures, and partnering with foundry and OSAT vendors. - Practical experience applying AI coding and agentic tools within engineering workflows.

Nice to have

- Masters or PhD in EE, CE, CS, or a related field, with a focus on VLSI test, fault tolerance and reliability, or EDA/CAD algorithms. - Experience with high-performance compute silicon such as ML accelerators, CPUs, GPUs, or large SoCs, including DFT for advanced packaging. - Product and test engineering depth in test program development, screens (HVS, HTOL), yield analytics, wafer-map correlation, outlier screening, and RMA failure analysis. - Experience building or extending AI-assisted design and verification flows with quantified gains. - Publications at major conferences (such as ITC, VTS, DAC, ICCAD, DATE) or open-source contributions in DFT, test, or AI for chip design.