DFT Engineer - Palo Alto
$160,000 - $230,000 USD yearly
Originally posted 23 September 2026 by the employer.
About the role
This role is responsible for ensuring the functionality, correctness, and quality of ASIC DFT logic by building verification environments and executing coverage-driven verification plans. The position covers DFT verification across scan/ATPG, JTAG, IJTAG (ICL/PDL), boundary scan, MBIST, memory repair, and fuseboxes.
What you'll do
- Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies. - Use EDA DFT tools such as TestMax and Tessent to create and run recommended pre-silicon test cases for inserted MBIST and scan fabric. - Develop directed test cases for non-vendor-supplied DFT logic and assist in verifying ATPG patterns, including SOC-level and manufacturing reset sequences. - Implement and track functional and code coverage, develop reusable verification components, and write SystemVerilog Assertions (SVA). - Analyze simulation results, debug verification and design issues, and perform root-cause analysis alongside DFT design engineers. - Automate regression testing and enhance verification infrastructure using Python and scripting, while supporting post-silicon test bring-up debug.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - 5+ years of experience in digital design verification, with at least 2 years in DFT verification specifically. - Strong hands-on experience with SystemVerilog and UVM-based or similar verification methodologies. - Experience with industry-standard EDA simulation tools such as Synopsys VCS, Siemens/Mentor Questa, or Cadence Xcelium. - Experience with EDA DFT tools including Synopsys TestMax + Yield Accelerator or Siemens Tessent. - Experience verifying test sequences for high-speed PHY logic, including PCIe and Ethernet (10G/40G/100G).
Nice to have
- Experience with change control systems, especially git. - Experience verifying SoC-level designs.
This role has been open 34 days — well below the 62-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
247
|
Median days open
62 d
|
Median salary
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Delos Data | All employers we track in this specialty (247 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 247 |
| Open roles in the wider Digital Design & Verification family | 3 | 3359 · 116 employers |
| Median days open | 34 d | 62 d (−28 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 36 open roles · median 48 d
- Qualcomm · 26 open roles · median 76 d
- NVIDIA · 21 open roles · median 45 d
- NXP Semiconductors · 19 open roles · median 50 d
- Synopsys · 16 open roles · median 30 d
- Intel Corporation · 10 open roles · median 55 d
How we counted: 247 open DFT Engineering (DFT Test) roles from 55 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.