DFT Engineer - Bengaluru, Karnataka, India
Verification, Validation & Test
$133,200 - $185,000 USD yearly
Originally posted 21 September 2026 by the employer — open 0 days.
About the role
This role involves architecting and delivering connectivity silicon for AI clusters.
What you'll do
- Own RTL design for assigned blocks from microarchitecture through synthesis sign-off.
- Develop high-quality, synthesizable Verilog/SystemVerilog.
- Drive design reviews, lint, CDC, and timing closure activities.
- Partner with architecture to translate specifications into microarchitecture.
- Collaborate with verification on testplans, coverage closure, and bug triage.
- Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
- 5+ years of digital design experience, including at least one full chip from spec to tapeout.
- Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows.
- Hands-on experience with timing closure, CDC, lint, and low-power design techniques.
- Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration.
Nice to have
- MS or PhD in Electrical Engineering or Computer Engineering.
- Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs.
- Familiarity with formal verification, emulation, or assertion-based methodologies.
- Background in advanced process nodes (7nm, 5nm, or below).
- Strong debug skills across pre-silicon and post-silicon environments.
Market context
This role has been open 0 days — well below the 60-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
214
|
Median days open
60 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (214 roles · 51 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 214 |
| Open roles in the wider Digital Design & Verification family | 52 | 3017 · 114 employers |
| Median days open | 104 d | 60 d (+44 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Who's hiring in this category
- AMD · 34 open roles · median 42 d
- Qualcomm · 25 open roles · median 80 d
- NVIDIA · 17 open roles · median 69 d
- NXP Semiconductors · 17 open roles · median 73 d
- Micron Technology · 10 open roles · median 112 d
- Synopsys · 8 open roles · median 46 d
How we counted: 214 open DFT Engineering (DFT Test) roles from 51 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.
Bengaluru, Karnataka, India
On-site
$133,200 - $185,000 USD yearly
14 days ago