DFT/DFx Architecture & RTL Lead - CA, Santa Clara, United States
Digital Design & SoC Architecture
Originally posted 5 October 2026 by the employer.
About the role
What you'll do
- Define and lead PHY-specific DFT/DFx architecture and methodology for SerDes, Memory PHY, and die-to-die interconnect IPs.
- Implement DFT/DFx features in RTL using Verilog/SystemVerilog.
- Support JTAG/IJTAG, ICL/PDL, scan compression, at-speed scan, and hierarchical DFT implementation.
- Support Siemens Tessent-based or equivalent industry-standard DFT flows for ATPG, pattern generation, and validation.
- Perform gate-level simulation and debug using tools such as Synopsys VCS and Verdi or comparable tools.
- Plan, implement, and verify MBIST-related features for embedded memories.
What you'll need
- Relevant industry experience in DFT, DFx, RTL design, semiconductor IP development, or SoC test methodology.
- Understanding of DFT architecture and micro-architectures, including scan, compression, test clocks, and test access mechanisms.
- Hands-on experience with Siemens Tessent DFT flows, such as Tessent Shell, Tessent Scan, Tessent ATPG, Tessent TestKompress, Tessent MemoryBIST, IJTAG, ICL/PDL, or Streaming Scan Network/SSN, or comparable tools.
- Hands-on RTL coding experience in Verilog and/or SystemVerilog.
- Experience with gate-level simulation, debug, and waveform analysis using tools such as Synopsys VCS and Verdi or comparable technologies.
- Understanding of MBIST planning, implementation, verification, and debug.
Nice to have
- Experience developing or supporting hierarchical DFT flows for complex SoCs or reusable IPs.
- Understanding of low-power design concepts such as power gating, multi-voltage domains, and isolation.
- Knowledge of common fault models, including stuck-at, transition, path delay, gate-exhaustive, IDDQ, and cell-aware fault models.
Market context
This role has been open 3 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1010
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1010 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 73 | 1010 |
| Open roles in the wider Digital Design & Verification family | 265 | 3176 · 114 employers |
| Median days open | 35 d | 62 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 143 open roles · median 60 d
- Synopsys · 82 open roles · median 24 d
- AMD (this employer) · 73 open roles · median 35 d
- Analog Devices · 48 open roles · median 40 d
- NXP Semiconductors · 48 open roles · median 77 d
- NVIDIA · 45 open roles · median 63 d
How we counted: 1010 open Digital/RTL Design (RTL Design) roles from 97 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.