Design Verification- Technical Leader - Greater Noida, India
Originally posted 11 September 2026 by the employer.
About the role
This role involves taking on a Technical Leader position within the Imaging verification team, driving verification strategy and closure for complex digital IPs in imaging and automotive subsystems.
What you'll do
- Own end-to-end verification strategy, planning, and closure for complex IPs/subsystems.
- Architect and review UVM-based verification environments, ensuring reusability and scalability.
- Drive functional and code coverage closure, define coverage models, and identify verification gaps.
- Lead protocol-level verification efforts (e.g., I3C, MIPI, AMBA), including VIP evaluation, integration, and debug.
- Apply formal verification techniques (e.g., JasperGold) to complement simulation-based verification.
- Mentor and technically guide junior verification engineers.
What you'll need
- 5-7 years of experience in digital design/IP verification, with ownership of verification closure for at least one complex IP or subsystem.
- Strong expertise in System Verilog and UVM methodology (testbench architecture, sequences, scoreboards, reference models).
- Proven experience with functional coverage, code coverage, and assertion-based verification (SVA).
- Hands-on experience with industry-standard simulation tools (VCS, Xcelium, or Questa) and debug tools.
- Experience with formal verification tools and methodology (e.g., JasperGold).
- Solid understanding of one or more protocols such as I3C, I2C, SPI, AMBA, MIPI-CSI, including VIP-based verification.
- Strong scripting skills (Python, Perl, or TCL) for automation, flow development, and regression management.
Nice to have
- Experience mentoring or technically leading a small team of verification engineers.
- Exposure to mutation testing or other coverage-quality assessment techniques.
- Familiarity with low-power verification (UPF/CPF) and Gate Level simulations.
- Experience working with EDA vendors (e.g., Cadence, Synopsys) for tool/methodology support.
- Prior contribution to internal verification methodology documents, guidelines, or reusable verification IP (VIP) development.
This role has been open 0 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1157
|
Median days open
63 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | STMicroelectronics | All employers we track in this specialty (1157 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 1157 |
| Open roles in the wider Digital Design & Verification family | 20 | 3079 · 114 employers |
| Median days open | 38 d | 63 d (−25 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Who's hiring in this category
- AMD · 101 open roles · median 38 d
- Qualcomm · 97 open roles · median 52 d
- NVIDIA · 85 open roles · median 70 d
- Synopsys · 65 open roles · median 23 d
- SiFive · 56 open roles · median 55 d
- NXP Semiconductors · 51 open roles · median 81 d
How we counted: 1157 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.