Design Verification Lead - Austin, Texas, United States
Originally posted 16 September 2026 by the employer.
About the role
This role involves leading design verification for an electronic IC from module-level simulation through SoC integration and gate-level signoff, extending into validation planning. The focus is on a unique architecture using silicon photonics and an active, programmable metasurface for matrix multiplications.
What you'll do
- Own verification methodology and testbench architecture, built on UVM with an emphasis on AI-driven flows.
- Build the verification plan across module-level simulation, SoC integration, interface checks, top-level IO, and validation plan.
- Specify, evaluate, and integrate third-party IP into the environment.
- Own gate-level simulation with SDF-annotated timing for tapeout closure.
- Extend the FPGA-based verification harness to exercise modules with real code.
- Stand up and operate the emulation environment, including provisioning and execution on cloud-hosted infrastructure.
- Use AI tooling to generate and iterate on testbenches and assertions, optimizing based on coverage feedback.
- Build and lead the verification team, partnering with system architecture, RTL design, physical design, DFT, and validation.
What you'll need
- 8 to 15 years in design verification, including leading verification on a GPU-class or complex compute ASIC through tapeout.
- Deep expertise in UVM and SystemVerilog, including ownership of testbench architecture, formal verification, coverage analysis, and CI/CD methodology.
- Gate-level simulation experience.
- Verification experience on a chip with many independently developed blocks and analog components, including integration of analog models.
- Comfort standing up a verification environment end-to-end, including emulation infrastructure.
- Breadth across the flow, from module-level simulation through SoC integration and into validation planning.
Nice to have
- Hands-on emulation experience, Palladium or equivalent.
- Development of analog models using WREAL or equivalent descriptions.
- FPGA-based verification or prototyping experience.
- Cadence toolchain experience.
- Exposure to silicon photonics or optical component verification.
Skills: UVM, SystemVerilog, testbench architecture, gate-level simulation, emulation, AI tooling
This role has been open 26 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1191
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Neurophos | All employers we track in this specialty (1191 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1191 |
| Open roles in the wider Digital Design & Verification family | 3 | 3166 · 114 employers |
| Median days open | 26 d | 64 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM, SystemVerilog, testbench architecture, gate-level simulation, emulation, AI tooling
Who's hiring in this category
- Qualcomm · 104 open roles · median 44 d
- AMD · 102 open roles · median 53 d
- NVIDIA · 77 open roles · median 66 d
- Synopsys · 61 open roles · median 29 d
- SiFive · 54 open roles · median 70 d
- Cadence Design Systems · 51 open roles · median 112 d
How we counted: 1191 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 13 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.