Design Verification Intern - VN - Da Nang, Vietnam
Originally posted 8 October 2026 by the employer.
About the role
As a Design Verification Intern, you will help verify IP designs before tape-out, learning modern verification methodology on real silicon-bound projects.
What you'll do
- Read and understand design specifications, and help create test plans and coverage plans.
- Study existing coverage group definitions and test cases, then write new tests, including constrained-random tests, to improve coverage.
- Run simulations, understand how the block under test operates, and debug failures.
- Work toward coverage improvement and closure.
- Contribute to improvements in the DV strategy, flow, and scripts.
- Collaborate with design engineers to resolve issues, and document verification results.
What you'll need
- Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Electrical & Computer Engineering (expected to graduate in 2027 or 2028).
- Familiar with Verilog and SystemVerilog.
- Good English.
- Strong debugging and problem-solving skills, and the ability to work well in a team.
Nice to have
- Knowledge of UVM.
- Experience with scripting languages such as Python or Perl, and a Linux working environment.
- Understanding of digital design fundamentals and mixed-signal design concepts.
Skills: Design Verification, test plans, coverage plans, Verilog and SystemVerilog, debug failures
This role has been open 0 days — well below the 62-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1206
|
Median days open
62 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (1206 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 1206 |
| Open roles in the wider Digital Design & Verification family | 32 | 3190 · 113 employers |
| Median days open | 27 d | 62 d (−35 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Design Verification, test plans, coverage plans, Verilog and SystemVerilog, debug failures
Who's hiring in this category
- AMD · 106 open roles · median 48 d
- Qualcomm · 104 open roles · median 43 d
- NVIDIA · 79 open roles · median 61 d
- Synopsys · 64 open roles · median 30 d
- SiFive · 55 open roles · median 65 d
- Cadence Design Systems · 52 open roles · median 108 d
How we counted: 1206 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 8 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.