Design Verification Engineer - SoC - Austin, United States
Originally posted 16 April 2026 by the employer.
Verify custom systolic arrays, DMA engines, and NoCs through SystemVerilog and Python-based performance modeling.
About the role
As a Design Verification Engineer on the Systems/Performance Verification team, you will verify custom IPs—including systolic arrays, DMA engines, and NoCs—for correctness and performance. You will validate hardware across pre-silicon and post-silicon phases in close collaboration with architecture, RTL, and software teams.
What you'll do
- Verify performance features of the design and correlate them with pre-silicon and post-silicon architectural performance models. - Develop test plans, test infrastructure, and tools for performance tuning, correlation, and verification. - Develop tests and checkers in SystemVerilog, Python, or vectors to debug and correlate RTL against performance models. - Build coverage monitors and analyze coverage metrics to ensure all design performance features are exercised. - Debug performance issues, analyze bottlenecks across hardware and software, and conduct performance tuning on silicon. - Improve and maintain architectural performance models while collaborating with software teams on workload efficiency.
What you'll need
- Strong understanding of digital design, RTL, and ASIC design flows. - Hands-on experience with performance verification, simulation, and modeling. - Experience developing checkers, coverage monitors, and testbenches in SystemVerilog. - Proficiency in Python for automation, data analysis, and performance modeling. - Experience building and maintaining performance models for chip subsystems, with an understanding of memory hierarchies, pipelines, interconnects, and compute accelerators. - Familiarity with performance bottleneck analysis, compiler optimizations, workload tuning, or kernel-level performance profiling tools.
Skills: performance verification, performance models, SystemVerilog, Python, coverage monitors, debug performance issues
This role has been open 192 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1259
|
Median days open
65 d
|
Median salary
$185k
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (1259 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 1259 |
| Open roles in the wider Digital Design & Verification family | 13 | 3310 · 115 employers |
| Median days open | 192 d | 65 d (+127 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: performance verification, performance models, SystemVerilog, Python, coverage monitors, debug performance issues
Who's hiring in this category
- Qualcomm · 120 open roles · median 44 d
- NVIDIA · 93 open roles · median 65 d
- AMD · 92 open roles · median 54 d
- Synopsys · 65 open roles · median 40 d
- SiFive · 55 open roles · median 82 d
- Cadence Design Systems · 52 open roles · median 124 d
How we counted: 1259 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.