Design Verification Engineer - San Jose, California, United States
$120,000 - $200,000 USD yearly
Originally posted 18 August 2026 by the employer.
Work on the RDU, SambaNova's chip for machine learning and AI workloads.
About the role
This role involves design verification of complex chip-level control and initialization features on the Reconfigurable Dataflow Unit (RDU).
What you'll do
- Develop and execute verification plans for chip-level control and initialization features.
- Develop SystemVerilog/UVM based verification environments, test sequences, checkers, assertions, and functional coverage.
- Verify sequencing, dependencies, state transitions, and recovery scenarios across multiple chip subsystems.
- Develop directed and constrained-random tests to identify architectural and implementation corner cases.
- Debug simulation and regression failures and work with design teams to root-cause and resolve issues.
- Analyze regression failures, functional and code coverage and drive verification to closure.
What you'll need
- 5+ years relevant industry experience.
- Strong proficiency in SystemVerilog and UVM.
- Experience with constrained-random verification, functional coverage, and assertion-based verification.
- Good understanding of chip initialization, control sequencing, clocking, and cross-domain interactions.
- Strong simulation debug and problem-solving skills.
- Proficiency in scripting languages such as Python, Perl, TCL, and shell scripting.
Nice to have
- Familiarity with CDC/RDC concepts and verification methodologies.
- Fluency in Claude / AI tools for verification development and debug.
Skills: verification plans, SystemVerilog/UVM, constrained-random verification, functional coverage, simulation debug
This role has been open 59 days — below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1195
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (1195 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1195 |
| Open roles in the wider Digital Design & Verification family | 7 | 3198 · 115 employers |
| Median days open | 59 d | 64 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: verification plans, SystemVerilog/UVM, constrained-random verification, functional coverage, simulation debug
Who's hiring in this category
- Qualcomm · 109 open roles · median 37 d
- AMD · 97 open roles · median 51 d
- NVIDIA · 84 open roles · median 58 d
- Synopsys · 63 open roles · median 31 d
- SiFive · 55 open roles · median 73 d
- Arm Holdings · 49 open roles · median 101 d
How we counted: 1195 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.