Design Verification Engineer - Mountain View, CA, United States
$200,000 - $300,000 USD yearly
Originally posted 19 May 2026 by the employer.
DensityAI is driving an AI accelerator program from first silicon through scale-out.
About the role
As a senior individual-contributor Design Verification Engineer, you will be responsible for end-to-end pre-silicon verification for complex IP, subsystems, and SoC system level verification from plan to functional closure. You will partner closely with hardware design and software teams, driving DensityAI's AI accelerator program.
What you'll do
- Own an entire testing domain based on your expertise
- Develop end-to-end testing strategy from IP to SOC-level and to emulation for our AI accelerator silicon
What you'll need
- 5+ years of experience in Block Level/Sub System Verification
- CPU Subsystem/IP integration or SoC/full-chip Verification
- Emulation testing or DMA/NoC Verification or Multi-SoC/Die to Die protocol verification
- Debug for functional closure of complex design or SOCs
- Proven records on end-to-end pre-silicon verification ownership and deliverables
- Well-versed in UVM methodology and testbench architecture
Nice to have
- RISC-V
- Formal verification
- Emulation platforms (Palladium, Veloce, or equivalent)
- Post-silicon bring-up
Skills: pre-silicon verification, IP, subsystems, SoC system level verification, UVM methodology, AI accelerator
This role has been open 34 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | DensityAI | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1192 |
| Open roles in the wider Digital Design & Verification family | 5 | 3191 · 115 employers |
| Median days open | 34 d | 65 d (−31 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: pre-silicon verification, IP, subsystems, SoC system level verification, UVM methodology, AI accelerator
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.