Design Verification Engineer — Memory Subsystem

Originally posted 17 August 2026 by the employer.

Qualcomm is seeking a Design Verification Engineer to join its memory subsystem verification team.

About the role

As a Design Verification Engineer, you will develop and execute comprehensive verification strategies for complex digital designs, including memory controllers, DDR/LPDDR/HBM, and custom memory interfaces within the memory subsystem. This role involves the complete verification lifecycle, from understanding design specifications to driving functional and code coverage closure.

What you'll do

• Develop verification strategies, test plans, and coverage plans for RTL designs.
• Build and maintain reusable SystemVerilog/UVM and formal verification environments.
• Create and execute constrained-random, directed, error-injection, and corner-case tests.
• Write and maintain SystemVerilog Assertions for protocol, interface, timing, and functional verification.
• Verify memory-controller, PHY-interface, and memory-subsystem functionality across multiple operating modes.
• Drive functional, code, assertion, and coverage closure.

What you'll need

• 3–10 years of experience in ASIC, SoC, IP, or subsystem design verification.
• Strong hands-on experience with Verilog, SystemVerilog, UVM, and SystemVerilog Assertions.
• Experience developing and debugging reusable UVM-based verification environments.
• Proficiency in developing UVM components such as sequences, drivers, monitors, scoreboards, agents, and functional coverage models.
• Experience with constrained-random verification and coverage-driven verification methodologies.
• Experience writing assertions for protocol compliance, temporal behavior, interface checking, and functional correctness.
• Strong understanding of digital design and verification fundamentals, including clocking, reset behavior, synchronous and asynchronous logic, and multi-clock-domain designs.
• Experience with simulation-based verification, waveform analysis, regression execution, and failure debug.

Nice to have

• Experience verifying LPDDR, DDR, DDR PHY, HBM, and custom memory interfaces.
• Familiarity with JEDEC memory specifications and memory-protocol requirements.
• Understanding of memory-controller, memory-subsystem, and PHY architecture.
• Experience with power-aware simulation using UPF.
• Knowledge of standard interfaces such as AXI, APB, AHB, DFI, or similar protocols.
• Experience with formal verification or assertion-based verification methodologies.
• Experience verifying high-performance, low-power, or multi-clock-domain designs.
• Experience with performance verification, including bandwidth, latency, throughput, efficiency, QoS, and stress testing of memory subsystems.
• Experience with memory training, initialization, refresh, power-management, frequency-switching, calibration, or error-handling scenarios.

Skills: verification strategies, test plans, SystemVerilog/UVM, functional coverage, memory-controller