Design Verification Engineer - Internal IP - Austin, United States
Originally posted 16 April 2026 by the employer.
Verify custom IPs including systolic arrays, DMA engines, and NoCs using UVM and SystemVerilog.
About the role
As a Design Verification Engineer on the Internal IP team, you will verify custom IPs powering hardware for inference workloads. The scope includes verifying systolic arrays, DMA engines, NoCs, and memory subsystems across the hardware-software stack.
What you'll do
- Develop and maintain UVM and SystemVerilog testbenches for compute arrays, DMAs, NoCs, and memory subsystems. - Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks. - Debug complex datapath and protocol issues in RTL and testbench environments. - Work closely with architects and designers to validate functionality and design intent. - Partner with software, firmware, and emulation teams to ensure end-to-end bring-up and debug coverage. - Contribute to reusable DV infrastructure, coverage models, and methodology improvements.
What you'll need
- Proficiency with UVM and SystemVerilog. - Debugging skills for complex digital designs. - Solid knowledge of computer architecture and digital design fundamentals. - Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
Skills: UVM, SystemVerilog, testbenches, verification plans, debug, logic designs
This role has been open 192 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1259
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (1259 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 1259 |
| Open roles in the wider Digital Design & Verification family | 13 | 3310 · 115 employers |
| Median days open | 192 d | 65 d (+127 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, testbenches, verification plans, debug, logic designs
Who's hiring in this category
- Qualcomm · 120 open roles · median 44 d
- NVIDIA · 93 open roles · median 65 d
- AMD · 92 open roles · median 54 d
- Synopsys · 65 open roles · median 40 d
- SiFive · 55 open roles · median 82 d
- Cadence Design Systems · 52 open roles · median 124 d
How we counted: 1259 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.