Design Verification Engineer - Interface IP - Austin, United States
Originally posted 16 April 2026 by the employer.
About the role
As a Design Verification Engineer on the Interface IP DV team, you will work with architects, designers, and vendors to ensure architecture requirements are met, validating correctness and performance across interface subsystems. This includes end-to-end verification ownership across IP subsystems such as PCIe, Ethernet, CPU subsystems, low-power peripherals, and sensors.
What you'll do
- Take end-to-end ownership of verification for one or more IP subsystems, including PCIe, Ethernet, CPU (ARC/ARM), low-power peripherals, or sensors. - Analyze vendor IP configurations and manage interface handshakes with the internal IP team. - Develop and maintain UVM- and SystemVerilog-based testbenches to verify functional correctness, performance, and compliance with IP specifications. - Collaborate with integration and SoC DV teams to ensure external IPs interact seamlessly within the broader chip architecture. - Drive coverage closure and sign-off by defining metrics, analyzing coverage holes, and running stress scenarios and corner-case verification.
What you'll need
- 5+ years of design verification experience. - Hands-on experience building scalable, reusable verification testbenches using SystemVerilog and UVM. - Direct verification experience with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs. - Ability to debug complex testbench failures and identify corner-case bugs across RTL and integration boundaries.
Skills: UVM, SystemVerilog, PCIe, Ethernet, coverage closure
This role has been open 192 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1259
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (1259 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 1259 |
| Open roles in the wider Digital Design & Verification family | 13 | 3310 · 115 employers |
| Median days open | 192 d | 65 d (+127 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, PCIe, Ethernet, coverage closure
Who's hiring in this category
- Qualcomm · 120 open roles · median 44 d
- NVIDIA · 93 open roles · median 65 d
- AMD · 92 open roles · median 54 d
- Synopsys · 65 open roles · median 40 d
- SiFive · 55 open roles · median 82 d
- Cadence Design Systems · 52 open roles · median 124 d
How we counted: 1259 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.