Design Verification Engineer (Einfochips) - San Jose, California (Cisco), United States
Originally posted 9 July 2026 by the employer.
About the role
This role requires a Design Verification Engineer to execute the complete verification cycle for client projects based on-site in San Jose, California.
What you'll do
- Execute the complete verification cycle including development of test plans, testbench components, stress and corner testing, failure debug, and coverage closure.
- Develop and integrate BFM, Driver, Monitor, and Scoreboard components within testbenches.
- Perform gate level simulations and write assertions for design verification.
- Drive verification closure alongside the engineering team.
- Report daily and weekly progress directly to clients.
What you'll need
- At least 6+ years of experience in System Verilog HVL and C++/C.
- At least 6+ years of experience in UVM.
- Proficiency in SVTB/UVM and C++ testbench environments.
- Proficiency in debug and assertions coding.
- Scripting experience with Make, Perl, Python, or related tools.
Nice to have
- Understanding of DSP.
- Experience with Subversion for repository management and Bugzilla.
Skills: System Verilog HVL, UVM, test plan development, BFM/Driver/Monitor/Scoreboard, coverage closure
This role has been open 149 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | eInfochips | All employers we track in this specialty (1254 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1254 |
| Open roles in the wider Digital Design & Verification family | 8 | 3328 · 115 employers |
| Median days open | 141 d | 64 d (+77 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: System Verilog HVL, UVM, test plan development, BFM/Driver/Monitor/Scoreboard, coverage closure
Who's hiring in this category
- Qualcomm · 120 open roles · median 43 d
- AMD · 94 open roles · median 53 d
- NVIDIA · 84 open roles · median 65 d
- Synopsys · 67 open roles · median 39 d
- SiFive · 55 open roles · median 81 d
- Cadence Design Systems · 52 open roles · median 123 d
How we counted: 1254 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.