Design Verification Engineer (eInfochips Inc) - US-CA-San Jose, California, United States
Originally posted 22 October 2026 by the employer.
Architect verification environments for ASIC SoC designs featuring ARM/RISC-V cores and AXI, NOC, Ethernet, PCIe, and UCIe protocols.
About the role
This role is responsible for architecting verification environments for ASIC SoC designs and delivering verification support from test planning through multi-million gate product tapeout. Technical scope spans verification of ARM and RISC-V processors, interconnect architectures, and protocols including AXI, NOC, Ethernet, PCIe, and UCIe.
What you'll do
- Architect verification environments for ASIC SoC designs, defining verification plans and supporting multi-million gate tapeouts. - Develop complex self-checking testbenches with constrained random stimulus generation. - Architect SoC test firmware, create test plan documentation, and develop and debug SoC ASIC platform test firmware in C/C++. - Implement and maintain integrated end-to-end formal verification flows to meet formal verification objectives. - Develop verification environments including environment assumptions, assertions, and cover properties aligned with the verification plan. - Develop and modify scripts to automate verification processes and execute regression and coverage closure.
What you'll need
- Typically a minimum of 8 years of related experience with a 4-year degree, 6 years with an advanced degree, or equivalent experience. - Strong SystemVerilog and UVM expertise. - Hands-on experience with AXI, NOC, Ethernet, PCIe, or UCIe switch architectures. - Experience with ARM or RISC-V CPUs along with C/C++ programming for SoC test firmware. - Experience with formal verification flows, assertions, cover properties, and regression and coverage closure. - Scripting experience to automate verification processes.
Skills: SystemVerilog, UVM, ASIC SoC, formal verification, testbench
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1233
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | eInfochips | All employers we track in this specialty (1233 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1233 |
| Open roles in the wider Digital Design & Verification family | 8 | 3298 · 115 employers |
| Median days open | 147 d | 64 d (+83 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, ASIC SoC, formal verification, testbench
Who's hiring in this category
- Qualcomm · 115 open roles · median 41 d
- AMD · 93 open roles · median 51 d
- NVIDIA · 84 open roles · median 62 d
- Synopsys · 66 open roles · median 37 d
- SiFive · 55 open roles · median 79 d
- Cadence Design Systems · 51 open roles · median 121 d
How we counted: 1233 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.