Design Verification Engineer(eInfochips Inc) - US-CA-San Jose, California, United States
$95,900 - $149,600 USD yearly
Originally posted 9 July 2026 by the employer.
About the role
Execute complete verification projects as a senior engineer, guiding verification methodologies and quality metrics across block, sub-system, and SoC top-level environments. The role involves hands-on verification of CPU sub-systems and protocols including PCIe, NVMe, NAND, and DDR.
What you'll do
- Execute complete verification projects with hands-on technical ownership, client interaction, and in-depth technical reviews. - Provide guidance to the team on developing UVM-based SV test-benches and defining block, sub-system, and SoC top-level test plans. - Verify sub-systems including PCIe, NVMe, NAND, DDR, and CPU sub-systems. - Drive regression execution and coverage closure. - Establish verification methodologies, flows, and quality metrics while contributing to process improvements. - Mentor junior engineers and provide technical guidance across verification tracks.
What you'll need
- 5–7 years of related experience with a 4-year degree, or 3 years with an advanced degree, or equivalent work experience. - Strong SV/UVM expertise. - Expertise in AXI, NOC, Ethernet, PCIe, or UCIe switch verification. - Experience with ARM or RISC-V CPUs along with C knowledge. - Hands-on experience developing UVM-based SV test-benches, writing test plans, and achieving coverage closure.
Skills: SV/UVM expertise, test-benches, test plans, regression, coverage closure
This role has been open 194 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1259
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | eInfochips | All employers we track in this specialty (1259 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1259 |
| Open roles in the wider Digital Design & Verification family | 8 | 3310 · 115 employers |
| Median days open | 142 d | 65 d (+77 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SV/UVM expertise, test-benches, test plans, regression, coverage closure
Who's hiring in this category
- Qualcomm · 120 open roles · median 44 d
- NVIDIA · 93 open roles · median 65 d
- AMD · 92 open roles · median 54 d
- Synopsys · 65 open roles · median 40 d
- SiFive · 55 open roles · median 82 d
- Cadence Design Systems · 52 open roles · median 124 d
How we counted: 1259 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.