Design Verification Engineer - Dallas, TX, United States
Originally posted 13 October 2026 by the employer.
About the role
This Design Verification Engineer role focuses on driving and defining design verification methodologies, tools, and flows to ensure that SoCs and IP meet functional and quality specifications. The role involves learning the SoC/IP functionality and system context to build comprehensive verification test plans for Multimedia, Vision, Data movement, interconnect, safety, security, and Realtime IPs.
What you'll do
- Architect and develop module and system-level test strategies, performance validation, and verification plans.
- Promote and advance verification methodologies for complex digital logic using C/UVM testbenches.
- Create, execute, enhance, and debug simulation test cases using coverage-driven, constrained-random stimulus.
- Define and implement functional coverage and drive coverage closure.
- Debug complex designs to identify the root cause of problems.
- Verify SoCs in emulation environments and perform post-silicon verification, characterization, and debug.
What you'll need
- 10+ years of experience in Design Verification (DV) or Design development.
- Expertise in data movement, SoC integration concepts, and bus protocols (e.g., AMBA: AXI, CHI, AHB, APB, etc.), with exposure to DMA, Cache, ARM CPU cores, and DDR.
- Proficiency in Verilog.
- Experience with simulation tools (e.g., NCsim), code coverage, and debug tools.
Nice to have
- Familiarity with verification environments to actively participate in functional debugging.
- Experience with SystemVerilog and VHDL.
- In-depth knowledge of bus protocols, including AXI, CHI, AHB, APB, and OCP.
- Proficiency in scripting languages such as Tcl, Perl, and Python.
- Experience with silicon debug using Automated Test Equipment (ATE) and bench characterization environments.
Skills: UVM testbenches, functional coverage, SystemVerilog, SoC/IP functionality, simulation test cases
This role has been open 1 day — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Texas Instruments | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 1192 |
| Open roles in the wider Digital Design & Verification family | 77 | 3191 · 115 employers |
| Median days open | 42 d | 65 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: UVM testbenches, functional coverage, SystemVerilog, SoC/IP functionality, simulation test cases
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.