Design Verification Engineer - California, Santa Clara, United States
$141,910 - $200,340 USD yearly
Originally posted 10 July 2026 by the employer. Relisted by the employer on 10 September 2026.
About the role
Intel is seeking a Design Verification Engineer for the Silicon Chassis team to contribute to the verification of interconnect and chassis IPs for SoC and platform products. You will work alongside senior engineers to build testbenches, write constrained-random tests, close functional coverage, and root-cause simulation failures.
What you'll do
- Develop testbench components, constrained-random stimulus, and functional checkers for interconnect and chassis IP under guidance of senior engineers. - Write, run, and debug simulation tests, analyzing failures and root-causing issues to closure with technical write-ups. - Contribute to functional coverage plans, coverage closure analysis, and regression triage. - Participate in spec reviews, design discussions, bug triage, and cross-boundary architecture, design, and software alignment. - Use AI-assisted coding and debugging tools as part of the development workflow to support team productivity through automation and scripting. - Continuously build depth in hardware design, verification methodology, and the chip development flow.
What you'll need
- BS or MS in Electrical Engineering, Computer Engineering, or Computer Science and 3+ months of internship experience in a hardware design or verification environment. - Foundation in logic design and digital circuits, including the ability to read and reason about RTL. - Demonstrated algorithmic thinking and software fundamentals application. - Demonstrated proficiency in at least one of C/C++, Python, or SystemVerilog through coursework, projects, or internships. - Coursework or project exposure to two or more of: computer architecture, parallel and distributed computing, operating systems, hardware/software interfaces, or VLSI design. - Demonstrated use of AI coding assistants as a regular productivity tool in coursework or project work.
Nice to have
- Coursework or project work in hardware verification, FPGA design, or RTL simulation (ModelSim, VCS, Questa, or similar). - Exposure to SystemVerilog, UVM concepts, or assertion-based verification through coursework, self-study, or internship. - Familiarity with standard bus protocols (AXI, AHB, PCIe) or cache/memory hierarchy concepts. - Demonstrated project work involving hardware modeling, algorithm implementation in HDL, or hardware-software co-design. - Comfort working in Linux environments, using version control (git), and writing build/test automation scripts. - Work experience in any related field.
Skills: verification plans, testbenches, UVM, SystemVerilog, formal verification
This role has been open 120 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1233
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (1233 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 1233 |
| Open roles in the wider Digital Design & Verification family | 99 | 3298 · 115 employers |
| Median days open | 36 d | 64 d (−28 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: verification plans, testbenches, UVM, SystemVerilog, formal verification
Who's hiring in this category
- Qualcomm · 115 open roles · median 41 d
- AMD · 93 open roles · median 51 d
- NVIDIA · 84 open roles · median 62 d
- Synopsys · 66 open roles · median 37 d
- SiFive · 55 open roles · median 79 d
- Cadence Design Systems · 51 open roles · median 121 d
How we counted: 1233 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.