Design Verification Engineer - CA, Santa Clara, United States
Originally posted 12 August 2026 by the employer.
Join AMD to drive verification of DDR interfaces for server memory products.
About the role
This includes advanced memory protocols such as DFI, DDR5, and LPDDR5/LPDDR6, across a range of DIMMs.
What you'll do
- Develop and execute verification plans for DDR5, LPDDR5, and DFI memory systems in server products.
- Comprehend the PHY's interaction in the complete system, including HW (Silicon), FW, BIOS, and SW, ensuring alignment to enable all features of the memory interface.
- Understand RTL and micro-architecture to engage in cross-functional discussions with IP/Domain architects and Design engineers for planning and debug.
- Contribute to verification methodology and knowledge sharing.
- Support Post-Si teams for Product Performance, Power, and functional issues debug/resolution.
What you'll need
- Advanced knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl.
- Experience developing and implementing SystemVerilog and UVM based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems.
- Experience working closely with hardware, firmware, and software teams to align on system-level memory architecture, identify integration issues, and define validation requirements.
- Strong proficiency in system verilog assertions, constraints, and coverage.
- Bachelor’s +8 years or Master’s degree +6 years in related discipline.
Nice to have
- Experience building VIPs and BFMs for memory interfaces from scratch.
- GLS, NLP, XPROP simulation experience.
- Experience in formal verification methods, with proven record of tool usage beyond the standard apps.
Skills: verification engineer, DDR interfaces, SystemVerilog, UVM, functional coverage models
This role has been open 65 days — slightly above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1205
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1205 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 96 | 1205 |
| Open roles in the wider Digital Design & Verification family | 251 | 3202 · 115 employers |
| Median days open | 51 d | 64 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: verification engineer, DDR interfaces, SystemVerilog, UVM, functional coverage models
Who's hiring in this category
- Qualcomm · 110 open roles · median 38 d
- AMD (this employer) · 96 open roles · median 51 d
- NVIDIA · 86 open roles · median 58 d
- Synopsys · 64 open roles · median 32 d
- SiFive · 55 open roles · median 74 d
- Cadence Design Systems · 50 open roles · median 116 d
How we counted: 1205 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.