Design Verification Engineer - Analog Mixed-Signal (AMS) | BCP - Santa Clara, CA, United States
Originally posted 25 September 2026 by the employer.
Work on Battery Charging Products.
About the role
This role involves defining, designing, modeling, and documenting digital cores for battery management devices within the Battery Charging Products group.
What you'll do
- Develop coverage-driven Verification Plans in collaboration with System, Application, and Analog Design teams.
- Create high-fidelity Analog behavioral models using Verilog-A, Verilog-AMS, Wreal (RNM) for top-level simulation.
- Build and enhance mixed signal testbenches using schematic, models, and RTL.
- Implement real-time analog checkers and post-processing checker strategies.
- Execute RTL and Gate Level Simulations (GLS), run regressions, and track functional coverage goals.
- Collaborate with Digital DV Team, Analog Designers, and Post-Silicon Validation teams to debug complex issues.
What you'll need
- Bachelor’s or master’s degree in electrical engineering (EE) or Electronics and Communication Engineering (ECE).
- Minimum 3 years of hands-on experience in Analog Mixed-Signal (AMS) design verification.
- Proficiency in analog behavioral modelling using System Verilog, Verilog-AMS, Verilog-A, or Wreal.
- Direct experience with mixed-signal verification involving schematic, behavioral models, and RTL.
- Strong command of Cadence Virtuoso/AMS Designer toolsets and debug environments.
- Ability to present technical analysis and conclusions to internal stakeholders and business leaders.
Nice to have
- Knowledge of UVM.
- Proficiency in scripting (Python, Perl, or Shell) to automate simulation flows and data analysis.
- Experience in signal processing, PMICs, or high-speed communication interfaces.
- Experience in silicon debug and working alongside silicon validation teams.
- Verification experience with I2C, SPI, UART protocols.
Skills: Analog Mixed-Signal (AMS) verification, Verilog-A, Verilog-AMS, mixed-signal testbenches, Cadence Virtuoso/AMS Designer, functional coverage
This role has been open 15 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1189
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Texas Instruments | All employers we track in this specialty (1189 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 26 | 1189 |
| Open roles in the wider Digital Design & Verification family | 76 | 3166 · 114 employers |
| Median days open | 38 d | 64 d (−26 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Analog Mixed-Signal (AMS) verification, Verilog-A, Verilog-AMS, mixed-signal testbenches, Cadence Virtuoso/AMS Designer, functional coverage
Who's hiring in this category
- Qualcomm · 106 open roles · median 43 d
- AMD · 103 open roles · median 50 d
- NVIDIA · 74 open roles · median 64 d
- Synopsys · 61 open roles · median 26 d
- SiFive · 54 open roles · median 67 d
- Cadence Design Systems · 51 open roles · median 109 d
How we counted: 1189 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.