Design Verification Engineer- AI Accelerator - Santa Clara, CA, United States

Originally posted 19 August 2026 by the employer.

Verify custom AI acceleration units including matrix and vector compute engines.

About the role

This role involves verifying and delivering Velaura's Physical AI SoC, working with architects, RTL engineers, software engineers, and system teams.

What you'll do

• Own verification of Velaura's custom AI acceleration units including matrix and vector compute engines.
• Work with architects to understand microarchitecture intent and create detailed test and coverage plans.
• Build verification environments using SystemVerilog, UVM, C, and C++ with portable stimulus, checkers, assertions, trackers, and coverage.
• Develop reference models for GEMM and GEMV operations and compare hardware results.
• Verify accelerator data flow including operand staging, tiling, accumulation, and result writeback.
• Verify precision, rounding, and quantization behavior against the architecture specification, and throughput, latency, utilization, and performance per watt under representative LLM and vision workloads.

What you'll need

• 8 or more years verifying high performance compute or complex digital designs.
• High level understanding of LLMs including transformer structure and inference data flow.
• Knowledge of GEMM and GEMV operations and how they map onto hardware.
• Experience with SystemVerilog, UVM, C, C++, assertions, and coverage driven verification.
• Experience building or using reference models in C, C++, or Python.
• Understanding of numerical formats and precision tradeoffs such as FP16, BF16, FP8, and INT8.
• Experience owning a block or unit of a design independently from test plan through coverage closure, including debug of complex failures.
• BS or higher in Computer Engineering, Electrical Engineering, or Computer Science.

Nice to have

• Prior experience porting LLM or neural network models to RTL and verifying them.
• Experience verifying a custom accelerator developed from scratch.
• Familiarity with systolic arrays, tensor cores, attention, KV cache, or mixture of experts hardware.
• Experience with PyTorch, ONNX, or compiler and runtime stacks for accelerators.
• Experience with formal verification, gate level simulation, or silicon bring up.
• Exposure to performance modeling, power analysis, profiling, and workload characterization.
• Familiarity with robotics, drones, autonomous vehicles, or edge AI systems.
• Experience using AI assisted verification workflows to improve productivity and coverage.

Skills: AI acceleration units, SystemVerilog, UVM, test and coverage plans, LLM