Design Verification Eng 2(IP/SoC) - United States
Originally posted 1 September 2026 by the employer.
Contribute to verifying complex FPGAs.
About the role
You will contribute to verifying complex FPGAs and integrate multiple sophisticated IP level Design and Verification (DV) environments.
What you'll do
- Integrate multiple sophisticated IP level Design and Verification (DV) environments.
- Craft highly reusable UVM TB.
- Implement effective coverage driven and directed test cases.
- Deploy new tools and implement methodologies to improve quality of tape-out readiness.
- Create IP level module and sub-system verification plans, TBs, portable test benches, sequences, and verification infrastructure.
- Develop UVM based highly reusable test benches for IP verification and achieve targeted coverage numbers.
What you'll need
- BS/MS Electrical Engineering, Computer Science, Computer Systems Engineering, or equivalent degree.
- 3+ years DV experience in IP/SoC verification.
- Proven track record of working full ASIC verification from concept to tape-out.
- Advanced knowledge of System Verilog and UVM methodology.
- Hands-on verification experience in verifying IPs like PCIExpress or Ethernet or USB in UVM environment.
- Hands-on verification experience in verifying IPs using AMBA bus architecture in UVM environment.
Nice to have
- Exposure on working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.
Skills: FPGA verification, UVM TB, System Verilog, IP/SoC verification, coverage driven
This role has been open 46 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1202
|
Median days open
65 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lattice Semiconductor | All employers we track in this specialty (1202 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 1202 |
| Open roles in the wider Digital Design & Verification family | 22 | 3202 · 115 employers |
| Median days open | 79 d | 65 d (+14 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: FPGA verification, UVM TB, System Verilog, IP/SoC verification, coverage driven
Who's hiring in this category
- Qualcomm · 110 open roles · median 39 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 84 open roles · median 59 d
- Synopsys · 64 open roles · median 33 d
- SiFive · 55 open roles · median 75 d
- Cadence Design Systems · 50 open roles · median 117 d
How we counted: 1202 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.