Design Verification Emulation, Hardware - Austin, TX, Palo Alto, CA, United States
$200,000 - $420,000 USD yearly
Originally posted 28 September 2026 by the employer.
About the role
This role involves driving IP and SoC verification on emulation platforms, translating architectural and microarchitectural definitions into emulation workloads.
What you'll do
- Translate IP and SoC verification plans into execution strategies, mapping tests to simulation, simulation acceleration, or emulator-hosted verification.
- Build and maintain models and test components for simulation acceleration and emulator-hosted verification flows.
- Develop and improve platform bring-up, compile, mapping, runtime, regression, and debug flows.
- Adapt or develop test environments, transactors, stimulus, and software-driven workloads for emulation platforms.
- Track workload execution and failures, review results with DV block owners, and provide emulation signoff.
- Triage emulation compile, runtime, and test failures, using traces, waveforms, and platform diagnostics to isolate issues.
- Build and apply agentic workflows across workload planning, model and test preparation, platform setup, run orchestration, failure triage, result analysis, and closure reporting.
- Build and maintain scripts and tools using Python, Tcl, Bash, or similar languages to improve platform usability, regression throughput, and results visibility.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, and 5+ years of industry experience.
- Hands-on experience with platforms such as Cadence Palladium/Protium, Synopsys ZeBu/HAPS, including bring-up, model integration, compilation, execution, and debug.
- Experience building or adapting models and test environments for simulation acceleration, emulator-hosted verification, or both.
- Strong understanding of verification planning, regression strategy, and verification closure.
- Experience verifying complex IP or SoCs.
- Proficiency in SystemVerilog, C/C++, and scripting languages such as Python, Tcl, or Bash.
- Ability to assess which tests and workloads are effective on emulation platforms.
Nice to have
- Experience using emulation for long-running software workloads, firmware and driver validation, system-level scenarios, or pre-silicon software bring-up.
- Background developing synthesizable test components, transactors, behavioral models, or emulation-friendly replacements for simulation models.
- Experience with UVM-based verification environments and adapting them for acceleration or emulation.
- Familiarity with coverage-driven verification and SystemVerilog Assertions (SVA).
- Experience using emulation workloads for performance verification and power estimation.
- Experience with high-performance silicon such as CPUs, GPUs, AI accelerators, or complex SoCs.
- Experience with workflow management, CI/CD, regression definition and visibility, EDA tool configuration and usage, and other infrastructure tasks.
Skills: emulation, Cadence Palladium, Synopsys ZeBu, SystemVerilog, verification planning, Python
This role has been open 11 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1189
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | River | All employers we track in this specialty (1189 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1189 |
| Open roles in the wider Digital Design & Verification family | 3 | 3166 · 114 employers |
| Median days open | 64 d | 64 d (same as this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: emulation, Cadence Palladium, Synopsys ZeBu, SystemVerilog, verification planning, Python
Who's hiring in this category
- Qualcomm · 106 open roles · median 43 d
- AMD · 103 open roles · median 50 d
- NVIDIA · 74 open roles · median 64 d
- Synopsys · 61 open roles · median 26 d
- SiFive · 54 open roles · median 67 d
- Cadence Design Systems · 51 open roles · median 109 d
How we counted: 1189 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.