Design for Test Lead - Austin, Texas, United States
Originally posted 18 September 2026 by the employer — open 2 days.
Neurophos uses silicon photonics and an active, programmable metasurface to perform matrix multiplications.
About the role
This role involves owning design-for-test for the electronic IC, setting the DFT strategy for the full chip, and overseeing coverage assessment and signoff. The work centers on chips that use silicon photonics instead of traditional electronic circuits to perform matrix multiplications.
What you'll do
- Own DFT architecture and test control design for multiple ASIC devices using ATPG scan (stuck-at/at-speed), MBIST, and boundary scan / JTAG, including MCM and external HBM memory module DFT capabilities.
- Architect on-die memory test, including controller specification and generation, pattern selection, RAM grouping and system test time and power analysis.
- Architect system level wafer and package level DFT plans for all phases of the product development process.
- Create and deploy integrated DFT development flow with critical metrics allowing quick analysis and updates to achieve near 100% test coverage.
- Own coverage assessment and signoff, including where to accept a coverage gap and the reasoning behind it.
- Develop and specify functional test vectors to augment structural coverage.
What you'll need
- 8 to 15 years in DFT, with hands-on ownership of scan, ATPG, and MBIST.
- Architect-level experience on a large digital ASIC: assessing a full chip, setting the DFT strategy, and owning coverage signoff.
- Experience developing and specifying functional test vectors to augment structural coverage.
- Track record through tapeout on a complex compute ASIC.
Nice to have
- Analog test specification experience: defining what it takes to test analog circuits and working directly with the analog team.
- Cadence toolchain experience.
- Exposure to silicon photonics test or design-for-test for photonic components.
- Experience using AI tooling in DFT flows.
This role has been open 1 day — well below the 59-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
216
|
Median days open
59 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Neurophos | All employers we track in this specialty (216 roles · 51 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 216 |
| Open roles in the wider Digital Design & Verification family | 3 | 3011 · 114 employers |
| Median days open | 1 d | 59 d (−58 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Who's hiring in this category
- AMD · 34 open roles · median 41 d
- Qualcomm · 25 open roles · median 79 d
- NVIDIA · 18 open roles · median 68 d
- NXP Semiconductors · 17 open roles · median 72 d
- Micron Technology · 10 open roles · median 111 d
- Synopsys · 8 open roles · median 45 d
How we counted: 216 open DFT Engineering (DFT Test) roles from 51 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.