Design for Test Intern, BS - Summer 2027
Verification, Validation & Test
Originally posted 4 September 2026 by the employer.
About the role
This internship involves designing and implementing Design-for-Test (DFT) solutions and reference flows for system-on-chip (SOC) designs.
What you'll do
- Understand design requirements and customer specifications.
- Learn and run computer-aided design (CAD) tools/flow for assigned designs.
- Design and develop SOC using Linux, TCL, Python/Perl, or other equivalent scripting languages.
- Analyze, debug, and implement DFT features using defined CAD tools/flow.
- Collaborate with global CAD teams on design flow fixes and feature improvements.
- Assist in design verification efforts using ICL/PDL constructs and SV/UVM.
What you'll need
- Currently enrolled in a Bachelor’s Degree in EE, CE, or a related field with an expected graduation date of Fall 2027 – Summer 2028.
- Fluent in English Language – written & verbal.
Nice to have
- Basic understanding of Linux/Unix/BSD Internals, with experience working on multi-threaded systems.
- Strong programming skills in scripting languages (e.g., TCL, Python) in a Unix type environment.
- Knowledge of SOC design flow and DFT practices, including At-Speed Test, Built-in Self-Test (BIST), Automated Test Pattern Generation (ATPG), IEEE1149.6 (AC-JTAG), and IEEE1687 (IJTAG).
Market context
This role has been open 24 days — well below the 64-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
221
|
Median days open
64 d
|
Median salary
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (221 roles · 51 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 221 |
| Open roles in the wider Digital Design & Verification family | 29 | 3113 · 115 employers |
| Median days open | 11 d | 64 d (−53 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 38 open roles · median 36 d
- Qualcomm · 23 open roles · median 88 d
- NXP Semiconductors · 20 open roles · median 51 d
- NVIDIA · 15 open roles · median 76 d
- Synopsys · 9 open roles · median 21 d
- Intel Corporation · 8 open roles · median 60 d
How we counted: 221 open DFT Engineering (DFT Test) roles from 51 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.