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Cadence Design Systems

Design Engineering Director

Cadence Design Systems AUSTIN, United States Full-time 7 months ago
Digital Design & SoC Architecture

Originally posted 27 April 2026 by the employer. Relisted by the employer on 11 November 2026.

About the role

Cadence Solutions (North America) team is looking for a Design Engineering Director to lead Front End Design projects.

What you'll do

  • Guide and mentor a team of RTL design engineers on Front End design projects.
  • Define and develop microarchitectural features for IPs and subsystems to meet PPA goals.
  • Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.
  • Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.
  • Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers.

What you'll need

  • 10+ years of Front End design and/or verification experience with a BS or MS in Engineering or Computer Sciences.
  • Proven experience in leading and managing complex engineering projects.
  • Experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration.
  • Expertise in RTL design (Verilog), simulators, and debuggers.
  • Hands-on experience in Synthesis, SDC creation, and supporting PD and STA teams.
  • Experience driving results in a multi-disciplinary organization.

Skills: Front End design, IP integration, RTL design, Verilog, Synthesis, SDC

More semiconductor jobs: Cadence Design Systems jobs · RTL design jobs

Market context

First seen in our index 197 days ago, well above the 65-day median for Digital/RTL Design roles.

Digital/RTL Design · RTL Design

Open roles in category
1098
Median days since first seen
65 d
Category median salary (all employers)
$188k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Cadence Design Systems compares in Digital/RTL Design hiring
Metric Cadence Design Systems All employers we track in this specialty (1098 roles · 104 employers)
Open roles in this specialty 22 1098
Open roles in the wider Digital Design & Verification family 120 3510 · 120 employers
Median days since first seen 149 d 65 d (−84 d vs this employer)
Median salary (USD postings) n/a $188k

Skills observed across this category: Front End design, IP integration, RTL design, Verilog, Synthesis, SDC

Who's hiring in this category

  • Qualcomm · 142 open roles · median 74 d
  • AMD · 92 open roles · median 55 d
  • Synopsys · 89 open roles · median 54 d
  • NVIDIA · 48 open roles · median 67 d
  • NXP Semiconductors · 45 open roles · median 110 d
  • Analog Devices · 40 open roles · median 57 d

How we counted: 1098 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.

Apply now
AUSTIN, United States
On-site
Full-time
7 months ago

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