Design Engineer - Timing Methodology
$143,800 - $230,000 USD yearly
Originally posted 19 August 2026 by the employer.
About the role
This role involves developing and modeling advanced timing sign-off methodologies for SOC and 3D/2.5D IC designs within Broadcom's Central Engineering Timing Sign-Off group.
What you'll do
- Develop and deploy timing signoff methodologies for advanced technology nodes.
- Design and implement SOC, 3D/2.5D IC & multi-die signoff solutions.
- Participate and Lead in EDA flow development for Primetime, Tempus & Innovus.
- Participate in complex studies and analysis of new concepts for solution design, development, and improvement.
What you'll need
- BS degree in EE/CS with 12+ years of industry experience, or MS/Ph.D. degree in EE/CS with 10+ years of industry experience.
- Hands-on experience in Timing Signoff methodology development.
- Hands-on experience in SOC and 3D/2.5D IC timing signoff.
- Hands-on experience with statistical data analysis and modeling.
- Hands-on experience with silicon technologies, testability and yield.
- Hands-on experience with industry standard STA tools such as Primetime and Tempus.
- Hands-on experience developing scripts in TCL, Python, Perl, Unix shell and flow automation.
- Experience with revision control, issue management/defect tracking, continuous integration, and continuous delivery/deployment tools.
Skills: timing sign-off, Primetime, Tempus, TCL, 3D/2.5D IC
This role has been open 58 days — well below the 73-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
683
|
Median days open
73 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (683 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 683 |
| Open roles in the wider Physical Implementation family | 38 | 1449 · 110 employers |
| Median days open | 157 d | 73 d (+84 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: timing sign-off, Primetime, Tempus, TCL, 3D/2.5D IC
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 169 d
- Synopsys · 63 open roles · median 39 d
- Micron Technology · 43 open roles · median 46 d
- Qualcomm · 38 open roles · median 73 d
- NVIDIA · 37 open roles · median 80 d
- GlobalFoundries · 33 open roles · median 36 d
How we counted: 683 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.