Design Engineer- (Standard and Custom Cell Characterization) -HBM - Richardson, TX, United States
Originally posted 29 June 2026 by the employer.
Characterize standard and custom cells across internal nodes and TSMC for High Bandwidth Memory (HBM) product lines.
About the role
The Design Infrastructure Engineer builds, enables, and scales characterization infrastructure and delivers generated IP across memory and logic developments. The position supports High Bandwidth Memory (HBM) product lines across Micron internal nodes and external foundries including TSMC.
What you'll do
- Develop and sustain scalable infrastructure for standard cell and custom cell characterization, covering timing, power, noise, and signal integrity modeling. - Build automated flows for multi-corner, multi-mode (MCMM) characterization across extensive PVT spaces, including Liberty model generation, validation, and regression frameworks. - Enable characterization across Micron internal nodes and external foundries such as TSMC, addressing variability, layout-dependent effects, aging, and reliability. - Support characterization for HBM core dies, custom base dies, and advanced 3D HBM architectures, partnering with design teams on TSV interfaces, PHY-critical paths, and high-speed datapath elements. - Integrate characterization flows into design, verification, and CAD environments to optimize model accuracy, turnaround time, and silicon correlation. - Lead root-cause debug and validation of mismatches among SPICE, extracted views, STA, and silicon behavior, creating metrics and automated checks for signoff.
What you'll need
- Bachelor's or Master’s Degree or equivalent experience in Electrical Engineering or a related field. - Strong fundamentals in CMOS digital and mixed-signal circuit development, device physics, and PVT variation. - Practical experience with standard or custom cell characterization procedures, including Liberty modeling (CCS/ECSM or equivalent) and SPICE-based simulation. - Solid understanding of STA flows and timing libraries. - Proficiency in scripting languages such as Python, Perl, or Tcl for automation.
Nice to have
- Experience in SiliconSmart or PrimeLib. - Experience working across multiple semiconductor process technologies. - Experience in HBM, DRAM, or high-speed interface development, particularly in environments involving advanced foundry PDKs such as TSMC nodes. - Familiarity with high-speed PHY development, TSV-aware considerations, and advanced modeling topics such as signal integrity, EMIR effects, aging, and reliability. - Prior exposure to infrastructure or methodology development beyond executing predefined flows. - Understanding of Agentic AI or willingness to learn Agentic AI to develop efficient workflows.
Skills: standard cell characterization, Liberty modeling, SPICE-based simulation, STA flows, scripting for automation
This role has been open 113 days — well above the 72-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
683
|
Median days open
72 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (683 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 46 | 683 |
| Open roles in the wider Physical Implementation family | 79 | 1464 · 110 employers |
| Median days open | 49 d | 72 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: standard cell characterization, Liberty modeling, SPICE-based simulation, STA flows, scripting for automation
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 149 d
- Synopsys · 62 open roles · median 40 d
- Micron Technology (this employer) · 46 open roles · median 49 d
- Qualcomm · 37 open roles · median 73 d
- GlobalFoundries · 36 open roles · median 28 d
- Keysight Technologies · 34 open roles · median 76 d
How we counted: 683 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.