Design Engineer (Low Power)
$176,300 - $264,500 USD yearly
Originally posted 23 February 2026 by the employer.
About the role
The Design Engineer (Low Power) develops technical specifications from architectural and systems requirements, delivering detailed low-power micro-architecture and designs for integrated wireless technologies. The work supports WiFi (802.11x) technology across the full ASIC development process from specification to post-silicon bring-up.
What you'll do
- Own design modules through the full ASIC development process, covering specification, RTL implementation, verification, synthesis, timing closure, emulation, and post-silicon bring-up. - Develop technical specifications from architectural and systems requirements to deliver low-power micro-architecture and implementation. - Partner with the verification team to define verification plans and actively participate in the debug phase. - Perform silicon power measurements, silicon debug, and power correlation against estimates. - Implement full-chip debug design utilizing ARM IPs.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 6+ years of ASIC design, verification, validation, integration, or related work experience (or Master's with 5+ years, or PhD with 4+ years). - 7 years of working experience in ASIC design, including 2 years of experience in low-power micro-architecture, design, power intent/implementation, power optimization, and power estimation. - Hands-on experience with silicon bring-up and debug. - Demonstrated experience with SoC micro architecture, multi-domain clocking, and AMBA bus protocols including AHB and APB. - Working knowledge of power analysis tools, power reduction techniques, and low-power methodology.
Nice to have
- Experience with AXI protocol. - Experience with ARM IP-based full-chip debug. - Experience with PCIe or USB peripherals. - Experience with CPU subsystem-based design. - Experience taking a low-power design from project start to volume chip production for at least one product cycle.
Skills: low power micro-architecture, RTL implementation, ASIC development process, silicon power measurements, ARM IPs, SoC micro architecture
This role has been open 200 days — well above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1083
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1083 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 158 | 1083 |
| Open roles in the wider Digital Design & Verification family | 420 | 3310 · 115 employers |
| Median days open | 61 d | 64 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: low power micro-architecture, RTL implementation, ASIC development process, silicon power measurements, ARM IPs, SoC micro architecture
Who's hiring in this category
- Qualcomm (this employer) · 160 open roles · median 61 d
- Synopsys · 87 open roles · median 37 d
- AMD · 77 open roles · median 43 d
- Analog Devices · 49 open roles · median 54 d
- NXP Semiconductors · 42 open roles · median 93 d
- NVIDIA · 40 open roles · median 64 d
How we counted: 1083 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.