Design Architect Analog IC Designer
Originally posted 24 August 2026 by the employer.
About the role
The Design Architect Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications. This role contributes to the design of long-reach SerDes.
What you'll do
- Design and develop analog/mixed signal IC circuit blocks.
- Contribute to the design of long-reach SerDes.
- Implement initial concepts and specifications through final verification.
What you'll need
- Minimum of 10 years of experience in the development of CMOS SerDes or high-speed I/O IC.
- Thorough understanding of jitter and signal equalization techniques.
- Proficient design experience in most of the following SerDes circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, ADC and DAC, Bias and Bandgap, and Voltage Regulators.
- Proficiency in using CAD tools for circuit simulation and post-layout verification.
- Design experience at ≥16Gbps and in ≤16nm technologies.
- MS or PhD in EE.
Nice to have
- Working knowledge of a set of common SerDes standards and their electrical requirements.
- Proficiency with layout entry.
- Cadence tool experience.
- Lab test experience.
Skills: SerDes, high-speed I/O, jitter, signal equalization, PLL
This role has been open 36 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 29 | 1385 · 107 employers |
| Median days open | 181 d | 76 d (+105 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SerDes, high-speed I/O, jitter, signal equalization, PLL
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems (this employer) · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.