DDR Validation Lead, Staff (AI Accelerator Platform) - San Diego, California, United States of America
$145,600 - $218,400 USD yearly
Originally posted 2 October 2026 by the employer.
Lead DDR validation for LPDDR5X/LPDDR6 memory subsystems on AI Accelerator platforms.
About the role
This role drives end-to-end validation of LPDDR5X and LPDDR6 memory subsystems. You will work on AI Accelerator and Flagship mobile platforms.
What you'll do
- Define and execute DDR validation strategy across emulation, FPGA, and silicon platforms.
- Drive LPDDR5X/LPDDR6 bring-up, training validation, frequency scaling, low-power state validation, and feature enablement.
- Develop and execute validation plans covering memory functionality, performance, reliability, power, and corner-case scenarios.
- Lead debug of DDR controller, PHY, firmware, SI/PI, timing, and system-level issues.
- Validate interactions between DDR, CPU, GPU, NPU, cache hierarchy, NoC, and system software.
- Drive bandwidth, latency, QoS, memory pressure, and AI workload characterization.
What you'll need
- BS, MS, or PhD in EE, CE, CS, or related field.
- 5 years of experience in DDR/memory subsystem validation or silicon bring-up.
- Strong understanding of LPDDR4/5/5X/6 architectures.
- Strong understanding of DDR controllers and PHYs.
- Strong understanding of memory training and calibration algorithms.
- Strong understanding of Cache, coherency, and NoC architectures.
- Strong understanding of Power management and low-power memory features.
- Strong post-silicon debug experience.
- Proficiency in C/C++ and low-level software development.
Nice to have
- Mobile SoC, AI compute, automotive, or server platform validation experience.
- Familiarity with SI/PI analysis, memory performance tuning, and thermal characterization.
- Experience driving first-silicon memory bring-up and volume production qualification.
Skills: DDR validation, LPDDR5X/LPDDR6, memory subsystem, silicon bring-up, memory training, post-silicon debug
This role has been open 7 days — well below the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
401
|
Median days open
41 d
|
Median salary
$174k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (401 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 34 | 401 |
| Open roles in the wider Silicon Validation & Test family | 132 | 2209 · 111 employers |
| Median days open | 27 d | 41 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $174k |
Skills observed across this category: DDR validation, LPDDR5X/LPDDR6, memory subsystem, silicon bring-up, memory training, post-silicon debug
Who's hiring in this category
- AMD · 56 open roles · median 51 d
- Micron Technology · 41 open roles · median 35 d
- Qualcomm (this employer) · 33 open roles · median 28 d
- Graphcore · 22 open roles · median 113 d
- NVIDIA · 21 open roles · median 28 d
- Microchip Technology · 20 open roles · median 66 d
How we counted: 401 open Post-Silicon Validation (Silicon Validation) roles from 63 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.