Data Center Structural Test Solutions Architect - TX, Austin, United States
Originally posted 18 August 2026 by the employer.
Develop and build methodology for DFT on AMD Instinct Accelerator solutions.
About the role
This is a lead engineering position responsible for developing and building methodology for DFT (Design for Test) on AMD Instinct Accelerator solutions, including test planning, pattern conversion, characterization/debug, and data analysis.
What you'll do
- Drive structural test coverage simulation and analysis from AOI, AXI, to ICT.
- Optimize the structural test plan to find SMT, PCB, and component issues.
- Develop test strategy for new product features, including identification, specification, design, and qualification of test fixtures, test equipment, and diagnostic software.
- Debug complex hardware and software issues during build phases.
- Contribute to automated diagnostic generation and validation infrastructure.
- Investigate and introduce new manufacturing test technology and methodology to improve production efficiency.
What you'll need
- Experience with a scripting language (Perl, Ruby, shell script, or similar).
- Proficiency in Unix/Linux environments.
- Solid Knowledge of IPMI, PCIE, BMC, and Thermal Solutions.
- Knowledge of at-speed testing, test insertion, test coverage assessment, test pattern development, fault simulation, debug, verification, designing and conducting experiments/tool evaluations.
- Ability to build and deploy generic DFT flows.
- Experience in ICT development capability, HW design understanding, board debug capabilities, and structured test understanding.
Nice to have
- Familiarity with IEEE standards such as 1500, 1149.1, 1687 and 1838.
- Experience in ICT fixture/tester setup, maintenance, and troubleshooting.
- Good knowledge of board manufacturing flow, PCB/fixture design.
- Debug experience in hardware, software, device, and/or manufacturing domains.
- Experience in XP, AGILE, Scrum, or Kanban as Scrum Master or Product Owner.
- Experience with revision control (GIT, SVN, CVS, RCS or similar).
- Experience with C++, Java, C, or C#.
- Familiarity with JTAG IEEE 1149.1 specifications.
This role has been open 59 days — well above the 29-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
553
|
Median days open
29 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (553 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 553 |
| Open roles in the wider Silicon Validation & Test family | 149 | 2226 · 113 employers |
| Median days open | 43 d | 29 d (+14 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Who's hiring in this category
- Teradyne · 76 open roles · median 23 d
- Renesas Electronics · 43 open roles · median 23 d
- Infineon Technologies · 41 open roles · median 39 d
- Micron Technology · 29 open roles · median 33 d
- Qualcomm · 28 open roles · median 29 d
- Texas Instruments · 23 open roles · median 24 d
How we counted: 553 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.