Data Center SoC Power & Limits Architect - San Diego, California, United States of America
$164,000 - $246,000 USD yearly
Originally posted 23 June 2026 by the employer.
About the role
The Data Center Power & Limits Architect defines and drives power management, thermal, and system limits architecture for compute platforms spanning SoC, server, rack, and cluster levels. This role architects end-to-end power and limits systems across silicon, platform, and data center infrastructure for AI and HPC workloads.
What you'll do
- Define holistic power, thermal, and electrical limits architectures across silicon, board, system, rack, and cluster levels. - Architect power budgeting, allocation, and enforcement mechanisms across CPU, GPU, memory, accelerators, and I/O. - Design dynamic power control and closed-loop control systems, including DVFS, DCVS, and AVS-like architectures, for proactive and reactive limits management. - Define requirements and interfaces for telemetry infrastructure, platform controllers, BMC, firmware, and system software to enable real-time monitoring. - Establish hardware/software partitioning for limits enforcement in collaboration with SoC architects, platform teams, software/firmware engineers, and data center infrastructure teams. - Build system-level models using MATLAB, Simulink, or architectural simulators to conduct workload-driven analysis and evaluate architectural trade-offs.
What you'll need
- Bachelor's degree in Science, Engineering, or related field with 6+ years of ASIC experience, Master's with 5+ years, or PhD with 4+ years. - 10 years of experience in power architecture, system architecture, or related domains. - Deep expertise in power management systems, limits control, DVFS/DCVS, power capping, and thermal/electrical constraints in high-performance systems. - Strong understanding of data center/server architecture covering CPU, GPU, accelerators, and memory systems. - Comprehensive knowledge of power delivery networks, including VRs, PDN, rack power distribution, and telemetry sensors. - Experience developing architectural models and analyses using tools such as MATLAB or Python.
Skills: power & limits architecture, silicon, board, system, rack, and cluster levels, power budgeting, allocation, and enforcement, dynamic power control systems, telemetry infrastructure, hardware/software partitioning
This role has been open 121 days — well above the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
479
|
Median days open
76 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (479 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 79 | 479 |
| Open roles in the wider Digital Design & Verification family | 413 | 3298 · 115 employers |
| Median days open | 85 d | 76 d (+9 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: power & limits architecture, silicon, board, system, rack, and cluster levels, power budgeting, allocation, and enforcement, dynamic power control systems, telemetry infrastructure, hardware/software partitioning
Who's hiring in this category
- Qualcomm (this employer) · 79 open roles · median 85 d
- NVIDIA · 54 open roles · median 71 d
- Apple · 38 open roles · median 14 d
- AMD · 35 open roles · median 71 d
- Arm Holdings · 27 open roles · median 119 d
- Micron Technology · 22 open roles · median 111 d
How we counted: 479 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.