Customer Engagement Engineer II - San Jose, United States
$105,000 - $195,000 USD yearly
Originally posted 23 September 2026 by the employer.
About the role
As an integral member of the HSV Customer Support Team, you will work with customers, field AE teams, and R&D groups to provide technical support for Cadence's Palladium, Protium, and Virtual Protocol (PDAPP) products.
What you'll do
- Handle incoming SFDC cases reported by field AEs and customers.
- Report tool bugs to R&D and work with field AE and customer to collect necessary collaterals and/or testcases.
- Test R&D fixes/patches.
- Track customer metrics in JIRA system and generate quality reports for management.
What you'll need
- BS-EE/CE with a minimum of 1 year experience in design and/or verification of complex digital designs, or Applications engineering/technical support role.
- General knowledge of design debug techniques and a strong understanding of logic design.
- Proficiency in HDL languages like Verilog, System Verilog, and VHDL.
- Proficiency in Unix/Linux scripting languages (ksh/bash/csh).
- Experience with emulation.
- General knowledge in TBA, SVA, SV coverage, and Low Power (UPF).
- General knowledge in PCIe, USB, and Ethernet protocol.
- Ability to communicate complex issues to internal teams and customers in a clear and concise manner.
Nice to have
- MS-EE/CE.
- Experience with Cadence's Palladium product.
- UVM experience.
Skills: technical support, Palladium, design debug, Verilog, System Verilog, emulation
This role has been open 17 days — well below the 81-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
690
|
Median days open
81 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (690 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 160 | 690 |
| Open roles in the wider Physical Implementation family | 183 | 1473 · 107 employers |
| Median days open | 168 d | 81 d (+87 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: technical support, Palladium, design debug, Verilog, System Verilog, emulation
Who's hiring in this category
- Cadence Design Systems (this employer) · 160 open roles · median 169 d
- Synopsys · 61 open roles · median 38 d
- Micron Technology · 42 open roles · median 91 d
- Qualcomm · 42 open roles · median 62 d
- NVIDIA · 41 open roles · median 75 d
- GlobalFoundries · 31 open roles · median 52 d
How we counted: 690 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.