CryoCMOS Digital IC Design engineer, Quantum - Austin, Texas, United States of America

Originally posted 28 September 2026 by the employer.

Develop advanced digital and mixed-signal integrated circuits and reusable IP for cryogenic CMOS and quantum systems.

About the role

This role involves developing advanced digital and mixed-signal integrated circuits and reusable IP for emerging semiconductor applications. You will focus on cryogenic CMOS and quantum systems.

What you'll do

• Design and develop digital CMOS circuits, digital subsystems, and reusable IP, including control, interface, timing, calibration, and signal-processing functions.
• Own digital IC development from microarchitecture and RTL implementation through functional verification, synthesis, timing closure, physical implementation, tapeout, and silicon validation.
• Develop and execute verification strategies using simulation, assertions, coverage, and regression methodologies.
• Perform and support synthesis, static timing analysis, clock/reset design, power analysis, design-for-test, and physical implementation activities, including post-layout verification and design signoff.
• Optimize digital architectures for power, performance, area, reliability, and operating-temperature requirements, including cryogenic operating conditions.
• Define silicon test and characterization requirements, analyze measured data, debug digital functionality and timing issues, and correlate silicon behavior with pre-silicon models and simulations.

What you'll need

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related field.
• Minimum 5 years of relevant digital integrated circuit or ASIC design experience.
• Demonstrated experience with RTL design and verification using Verilog, SystemVerilog, VHDL.
• Experience with ASIC design flows including synthesis, static timing analysis, clock/reset methodology, design-for-test, physical implementation, timing closure, and signoff.
• Strong understanding of synchronous digital design, clock-domain crossing, reset-domain crossing, low-power design concepts, and PVT-related timing behavior.
• Proficiency with industry-standard digital design, verification, implementation, and analysis tools and the ability to independently debug complex pre-silicon and silicon issues.

Nice to have

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
• Experience with cryogenic CMOS, quantum-control electronics, mixed-signal SoCs, high-speed interfaces, or other advanced digital applications.
• Experience with digital standard-cell libraries, characterization, timing/power models, or digital-flow enablement for new semiconductor technologies.
• Familiarity with formal verification, UVM, FPGA prototyping, DFT/scan, memory interfaces, processors, DSP, serializers/deserializers, or high-speed digital architectures.
• Experience with silicon bring-up, characterization, and correlation of measured results to RTL, gate-level, timing, or power models.
• Familiarity with design and verification automation using Python, Tcl, Perl.

Skills: digital CMOS circuits, RTL implementation, functional verification, synthesis, timing closure, design-for-test