CPU Verification Fellow, RISC-V High-Performance Processor - Austin, Texas, United States
$100,000 - $500,000 USD yearly
Originally posted 28 May 2026 by the employer.
About the role
Tenstorrent is seeking a CPU Verification Fellow to lead verification strategy and execution for RISC-V high-performance processors. This technical leadership role covers out-of-order, speculative, superscalar CPUs across simulation, formal verification, emulation, FPGA, and silicon bring-up.
What you'll do
- Own verification strategy and planning for RISC-V high-performance superscalar CPUs, subsystems, and out-of-order microarchitectures. - Build and scale test plans, functional coverage, checkers, assertions, scoreboards, and constrained-random environments. - Verify CPU core features including frontend, branch prediction, rename, scheduling, execution, load-store, memory ordering, cache hierarchy, retirement, exceptions, interrupts, debug, and coherency interactions. - Define scalable verification methodology across simulation, formal verification, emulation, FPGA prototyping, and silicon bring-up. - Partner cross-functionally with architecture, RTL, performance modeling, SoC, firmware, compiler, and validation teams while mentoring senior engineers.
What you'll need
- Experience verifying high-performance superscalar CPUs, including out-of-order and speculative processors. - Knowledge of RISC-V architecture, covering ISA compliance, privileged architecture, virtual memory, atomics, vector extensions, and memory model behavior. - Proficiency in SystemVerilog, UVM, constrained-random verification, assertions, functional coverage, and advanced debug methodologies. - Hands-on experience with CPU reference models, instruction generators, ISS-based checking, or differential testing. - Practical expertise with formal verification and large-scale CPU verification environments.
Skills: CPU verification, RISC-V, SystemVerilog, UVM, constrained-random verification, formal verification
This role has been open 149 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tenstorrent | All employers we track in this specialty (1254 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 1254 |
| Open roles in the wider Digital Design & Verification family | 26 | 3328 · 115 employers |
| Median days open | 149 d | 64 d (+85 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: CPU verification, RISC-V, SystemVerilog, UVM, constrained-random verification, formal verification
Who's hiring in this category
- Qualcomm · 120 open roles · median 43 d
- AMD · 94 open roles · median 53 d
- NVIDIA · 84 open roles · median 65 d
- Synopsys · 67 open roles · median 39 d
- SiFive · 55 open roles · median 81 d
- Cadence Design Systems · 52 open roles · median 123 d
How we counted: 1254 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.