CPU Verification Engineer (RISC-V) - Santa Clara, California, United States of America

Originally posted 7 May 2026 by the employer.

Targeting RISC-V CPU verification across cache coherence, memory ordering, and speculative execution.

About the role

As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will verify selected parts of the CPU design to ensure functionality for product launch.

What you'll do

- Work with CPU and SOC Architects to understand concepts and high-level system requirements. - Develop detailed Test and Coverage plans based on architecture and micro-architecture specifications. - Build verification environments and components, including stimulus, checkers, assertions, trackers, and coverage. - Develop verification plans and testbenches for your assigned functional domain. - Execute verification plans, handling design bring-up, DV environment bring-up, regressions, and debug of test failures. - Track and report DV progress using metrics including bugs and coverage.

What you'll need

- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of hardware engineering, software engineering, or related experience (or Master's degree and 3+ years, or PhD and 2+ years). - Experience in hardware engineering, systems engineering, or software engineering within microprocessor or chip design environments. - Ability to develop and work independently on a block or unit of the design.

Nice to have

- Extensive knowledge of industry Instruction Set Architectures, particularly RISC-V. - Deep knowledge of micro-processor verification functions and architectures, such as cache coherence, memory ordering and consistency, prefetching, branch prediction, renaming, speculative execution, and address translation/memory management. - Knowledge of Random Instruction Sequencing (RIS) and testing designs at block/unit and subsystem/chip levels. - Experience writing test plans, portable testbenches, transactors, and assembly code. - Experience with verification methodologies and tools such as simulators, coverage collection, gate-level simulation, waveform viewers, and mixed-signal verification. - Experience with formal verification, assertions, silicon bringup, or leading a small team of verification engineers performing CPU verification.

Skills: RISC-V, Test and Coverage plans, Verification environment, CPU verification, Cache Coherence, Memory ordering