CPU System and Compute Die Architect - Austin, Texas, United States of America
$211,900 - $317,900 USD yearly
Originally posted 14 May 2026 by the employer.
About the role
This role focuses on CPU system architecture and micro-architecture definition across interrupts, timers, address maps, coherent and non-coherent NoC protocols, debug, and RAS mechanisms. You will evaluate the impacts of multi-die compute systems to deliver high-performance, low-power server-class computing platforms.
What you'll do
- Collaborate with chip architects to translate high-level system requirements and architectural concepts into CPU system specifications.
- Develop High-Level Architecture and Micro-Architecture specifications that translate directly into RTL design.
- Take a leadership role in developing the micro-architecture and design of high-performance CPU systems across data, control, and debug features.
- Partner with hardware, software, and firmware teams to establish end-to-end CPU system architecture and define control loops.
- Conduct performance exploration and define high-performance strategies in coordination with the CPU modeling team.
- Prepare and present comprehensive technical documentation for engineering teams, senior management, and internal partners.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 8+ years of engineering experience (or Master's degree with 7+ years, or PhD with 6+ years).
- Deep technical knowledge of microprocessor architecture, including interconnect protocols, timer synchronization, interrupt controllers, and configuration access protocols.
- Experience with multi-die CPU compute architectures, multi-die system complexities, and die-to-die channels.
- Expertise in RAS mechanisms, safety mechanisms, and telemetry architecture for power and performance monitoring.
- Proven experience defining architecture and micro-architecture for debug and trace, scan-dump, memory dump mechanisms, and DFx technologies.
- Understanding of logic design principles, including timing and power implications, as well as software and firmware control loops.
Nice to have
- Master's degree in Computer or Electrical Engineering.
- Understanding of CPU and cluster architecture.
- Understanding of high-performance and low-power micro-architecture techniques and trade-offs in CPU microarchitecture.
Skills: CPU architecture, SoC architecture, micro-architecture, multi-die system, RAS, Debug and Trace
This role has been open 162 days — well above the 78-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
473
|
Median days open
78 d
|
Median salary
$239k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (473 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 80 | 473 |
| Open roles in the wider Digital Design & Verification family | 424 | 3328 · 115 employers |
| Median days open | 83 d | 78 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $239k |
Skills observed across this category: CPU architecture, SoC architecture, micro-architecture, multi-die system, RAS, Debug and Trace
Who's hiring in this category
- Qualcomm (this employer) · 80 open roles · median 82 d
- NVIDIA · 52 open roles · median 69 d
- Apple · 37 open roles · median 16 d
- AMD · 36 open roles · median 73 d
- Arm Holdings · 27 open roles · median 121 d
- Micron Technology · 21 open roles · median 100 d
How we counted: 473 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.